jecel

The first couple of models used TTLs for the video circuit. These were replaced with the 6845 later on.

As far as I know the bulk of the Boston Museum was put on a train to California where it became the start of the Computer History Museum.

https://en.wikipedia.org/wiki/Computer_History_Museum

Some more details about Brazil - all imports were banned at the time to deal with the external debt crises. What was special about micro and mini computers was that foreign companies were forbidden from making them locally and selling them (like the did with cars, electronic goods and many other products). So clones dominated the market completely.

The Sinclair and TRS-80 clones arrived in 1981, the Apple II in 1982 and the PC XT in 1983 (at the absurd cost of US$15K for a configuration that would be US$5K in the US. This dropped to around US$3K by late 1984 for a configuration of similar price as the US, so not the "many times more expensive" that most people remember). There were very few TRS Color Computer clones, a single Sinclair Spectrum and the single Macintosh clone was not never authorized (every computer launch had to be approved by the government). The two MSX officially arrived in 1985 but sales actually started in 1986. The PC AT clones only started selling in 1987 and 386 machines in 1989 - these were the longest delays of all. An even longer delay was in PC graphics, which were stuck at CGA from 1983 all the way to 1992 (with imports allowed there was a jump to VGA+Multisync).

With the exception of the Spectrum and Mac clones by companies that had invested heavily in their predecessors, nobody tried to copy machines with custom chips, so no Ataris, Commodore 64s, Amigas, etc. The Commodore Pet would have been easy to clone, but there was no preexisting market of contraband machines due to the awkwardness of lugging the built-in monitor.

After the reserved policy ended in 1991 a company called PCI do Amazonas brought the Amiga to Brazil and was officially still making the A1200 months after Commodore itself had shut down. So we did get one of the three 68000 machines, even if very late.

Both stories are true as the microwave oven was invented twice independently.

This article has July 18, 1957 as the date for the Univac 120's arrival in Brazil: https://comp.ita.br/iec/

Most other sources just mention the year.

Jef considered holding down a key to be a "quasi mode". It is like the difference between the shift key and the caps lock key.

Rasking recommended cancelling searches by mashing the keyboard randomly to extend what you had typed so far with something that was sure to not be found in your text. The search advances with each new key you type while holding "leap". I agree that this was not discoverable at all, though it is trivial to learn. I don't know if backspacing while leaping would backtrack the search, but if that was the case it would have been what I would have tried (this would be just a little slower than Jef's suggestion).

Algol 68, APL, AWK, COBOL, Fortran, Julia, Mathematica and Wolfram Language, MATLAB and Octave, PL/I, RPG, R, Smalltalk, etc (including Lua).

In the SOAR all instructions could be tagged or not (the % bit selected this). They then tested the effectiveness of this (Patterson's "quantitative approach") by changing their compiler to output non tagged versions of a given instruction with explicit software checking and then comparing the results of several benchmarks with the same code using the tagged instructions. It turned out that only the tagged ADD had a measurable result.

So when the SPARC was created it included a TADD instruction. It also had a TSUB for symmetry even though the SOAR guys showed it didn't really help. The tags were moved from the top bit on SOAR to the bottom two bits in SPARC. Unfortunately exception handling on 32 bit SPARCs was really slow so pure software alternatives actually performed better. This exception handling problem also made register windows far less interesting than they had been in the Berkeley designs (this was improved in SPARC v9).

If a computer can emulate another computer that is known to be Turing complete then it must itself be considered Turing complete. One thing we must decide is if we allow the addition of memory that the first machine didn't have originally. For example, an Apple ][ can emulate a modern PC (at a tiny fraction of the speed) if we can add a card with a few GB of RAM to it.

A very simple Von Neumann style computer is the ByteByteJump. It has a single instruction (so no op code) with 3 address fields and it copies a single byte from the first address to the second address and then always jumps to the third address. If the addresses are 3 bytes long then every instruction takes up 9 bytes in memory. You can do math and logic operations by setting up 16KB tables in memory and then patching an instruction so the two operands are the bottom two bytes of the first address. To subtract the byte in address 0x001234 from the byte in address 0x00C0F0 and store the result in address 0x003333 on a little endian BBJ with a subtraction table at 0xD00000 you could use this sequence:

  0x100: 0x001234 0x000112 0x000109
  0x109: 0x00C0F0 0x000113 0x000112
  0x112: 0xD00000 0x003333 0x00011B
  0x11B:

There are several ways of implementing conditional jumps by patching the value of the third address.

Could the Z3 emulate this machine if given a 16MB memory it could interface to? Its instruction tape could be made into an infinite loop, which is good enough for this application. There are no other jumps or conditional execution in the emulator.

If you do need conditional execution to emulate a Turing complete machine (the Game Of Life, for example) then you might get by with conditional assignment instead. If the value of B is either 0 or 1, then Z:=A*B+C(1-B) will assign either A or C to Z. I am not familiar enough with the Z3 but would be surprised if it can't even do that.

About the Z80 pricing, in 1981 I was able to buy a Z80A and two PIO chips for $3 each in Brazil (lots of taxes). Some of the larger TTL chips (like bidirectional buffers) cost more than that, so when a group asked me to design a CP/M computer in 1984 I actually added extra Z80s (to generate video and for the two GPIB interfaces) to save TTLs.

HyperCard itself would not have had the role it did if Apple hadn't bundled it with every Mac. This is sort of like the Basic that came with older computers - any language that you had to get separately would get a tiny fraction of the popularity of the default option.

EToys and Scratch were made by the same people but with different goals. EToys was made to allow children to express scientific ideas while Scratch was made to allow the participants of MIT's Media Lab computer clubhouses to express themselves creatively as part of the remix culture.

In EToys, as in the earlier Vivarium project, children were supposed to create all their own objects from scratch (ironically). In Scratch the use of clip art, scanned material and other people's project is encouraged. In fact, "scratch" is a dj term for a certain way of mixing music. I can't find the exact definition since Google insists on pointing me to the software instead.

I think the 8086 has 117 instructions. It is a good example of a CISC, after all, with instructions like the one capable of copying a C string: REPNZ MOVSB.

While I have seen many claims that the 8086 has more than 20 thousand instructions that is very silly. By the same criteria any RISC with fixed 32 bit instructions would have 4 billion of them.

I compared the sizes of several processors[1] including these RISC-V: Glacial, SERV, PicoRV32, VexRiscv and Darkriscv. Compiled to NAND gates the results were 2063, 3595, 34463, 49214 and 50424 gates respectively. Multiply these numbers by 4 to know how many transistors a CMOS implementation would need.

I also implemented them in a bunch of different FPGAs, though that is less relevant here.

Glacial is an 8 bit processor optimized to emulate a 32 bit RISC-V and SERV is a serial implementation of a 32 bit RISC-V. They save transistors at the cost of many clocks per instruction.

There are several projects that implement RISC-V using TTLs but I have not heard of one using individual transistors.

[1] https://www.mdpi.com/2079-9292/13/4/781

I have an old list of Smalltalk computers (most links probably won't work):

http://www.merlintec.com/swiki/hardware/26.html

I also mention the list of Java processors in that page.

You are correct as is the other reply to my post. The chip in chapter 3 of the 1977 "The Bipolar Microcomputer Components Data Book" from Texas Instruments is the SBP9900 processor, not the TMS9900. I had never noticed this detail before and always had used this book as my reference for the 9900.

The TMS9900 was made in I²L bipolar technology, not MOS. Texas Instruments also had a 4 wide bitslice using the same fabrication process.

Thanks! I still design Smalltalk computers like I did back then but now I also design my own processors.

That is probably similar to how you could use both sides of a single sided floppy. Both sides were tested and the factory ended up with a huge pile of floppies that passed both sides and a small pile that failed one side (and some that failed both sides and were discarded). The market wanted more single sided disks so they simply moved a number of floppies from the first pile to the second. That meant that you mostly likely got a double sided product when you paid for a single sided one. But it was a risk.

Same thing of processor and memory speed bins.

A 4116 DRAM chip with a 250 ns access time would have a 500 ns cycle time, so could read or write 2 million words per second. The Acorn people called this a 2 MHz memory. You could have shorter cycle times in "column mode" where you pulsed the /CAS signal only to access words in the same row and the Acorn designers made good use of that for the Electron (reading 8 bits from a 4 bit wide memory) and the ARM based Archimedes (fetching instructions other than jump, load or store as well as loading the video and audio FIFOs).

From one DRAM generation to the next the cycle time might be different for chips with the same access time. This allowed me to make the 512KB Macintosh faster than the 128KB one (http://www.merlintec.com/lsi/mac512.html).

It is interesting that the MIPI, PCIe and Serdes columns in the table of device models is "-" for all of them. That is the case for the other Titanium family and nothing is mentioned about Serdes in the datasheet, only in the text description and table for the whole family.

To nitpick, FPGAs are COTS (Commercial Off The Shelf) components since a single FPGA can be bought to be used in a huge number of different products. An Application Specific Integrated Circuit is designed for use in a single product, as the name says. A classic example were the two big chips Apple designed for the Apple //e to replace the large number of TTLs used by the Apple ][+.

To be fair, more people use the term ASIC wrong than right.

The date I have for that work is 1997. See my old list of Smalltalk computers:

http://www.merlintec.com/swiki/hardware/26.html

Exactly - it was $500 for Plan 9 versus $0 for Linux which included all the sources until nobody was interested in Plan 9 anymore.

If you consider the evolution IBM 801 -> ROMP -> POWER -> PowerPC then you might say the that the roots of the PowerPC are from 1975, or 1982, or 1990 or 1991 and you would have a valid point in all cases.

But it is very reasonable to consider ARM older than PowerPC.

And it is the successor to DEL (Data Entry Language) and SOL (Simple Object Language). Since 'Sol' is 'Sun' in Portuguese, they decided it would make sense to move to Moon.

Cray didn't believe in caches or virtual memory. He felt that data placement and movement should be 100% in the programmer's control.

8MB was the main memory, but it was made from really high speed (and super expensive!) static RAM chips instead of the dynamic RAMs most other machines used. Other machines used SRAMs for caches, so I guess you could consider the Cray 1's main memory to be a cache.

The Cray had 8 "A" address registers but also 64 "B" registers. In the same way you had 8 "S" scalar registers plus 64 "T" registers. The main memory was highly interleaved so you could very quickly load and save blocks of B and T registers as well as the vector registers. You can think of B as a sort of cache for A and T as a sort of cache for S, but you had to explicitly handle this in your program.

While the tool creates the chip by placing at the gate level, the designs themselves can be studied at the transistor level if you want. You can study the actual chip gds file or look up the gds for each standard cell individually.

There was a Squeak web browser plugin early on so you could run Etoys or Scratch that way. Unfortunately they found out that schools had a very short list of browser plugins they allowed on their computers. Flash was included, Squeak was not. They failed to change that after years of trying.

This motivated the MIT guys to port Scratch to Flash (very bad timing) and the ex Squeak guys to focus on Javascript (Lively Kernel and other projects).