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It is interesting that the MIPI, PCIe and Serdes columns in the table of device models is "-" for all of them. That is the case for the other Titanium family and nothing is mentioned about Serdes in the datasheet, only in the text description and table for the whole family.

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The other Efinix chips are still sold as "has serdes" yet have not a single mention of it in the datasheets. At first I thought it was because they're still going through silicon qualification, but it's been 18 months and they're still TBD.

Forgot to add, over that time frame that DID add MIPI documentation so they've got that working.

May be, because could implement in FPGA.

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