Efinix Titanium Ti375 FPGA offers quad-core hardened RISC-V, PCIe Gen 4, 10GbE | Hacker News Reader

Efinix Titanium Ti375 FPGA offers quad-core hardened RISC-V, PCIe Gen 4, 10GbE

cnx-software.com

42 pointsmikhael14 comments

Wtf is a "Quantum compute fabric", and why is it called that despite this chip having apparently exactly nothing to do with quantum computing? This looks to be a "plain simple" FPGA, making this just about the worst misnomer (or even false advertising) I've ever seen‽

https://www.efinixinc.com/technology.html

Looks like the 4 CPUs are hardened versions of the VexRiscv cores that were already used as soft cores in their previous FPGA product line.

If I had to design my own FPGA, I would probably make the same choice. It’s one of the best CPUs out there in terms of area/performance/functionality and available under an MIT license.

What is the difference between a hard and soft core?

A hard-core is hardware baked into the silicone of the FPGA from the fab in addition to the programable gates on board and is therefore faster and more space and energy efficient, soft-core is software synthesized from HDL code and programed into the FPGA using its available gates, making it slower and less eficient.

"Hard" refers to components that are actually part of the ASICs and exist on the die. For example, a "hard DDR memory controller" means that there is a physical part of the die that implements the DDR spec.

"Soft" refers to components that run on top of an FPGA. A "Soft CPU" is a CPU that runs on the FPGA, and is not part of the actual physical design.

It depends. Exists few levels, to know exactly need more information.

Mostly used in modern tech types 1 and 3a from my comment, but large scale production CPU SOCs usually 3b or hybrid 3b with 2, and sometimes you could found type 2 in consumer electronics or for example in routers (because cheap in range of few thousands chips; 3b effective for millions+; 3a in range from 50k to millions).

Sometimes also used Application-specific instruction set processor (ASIP), as I know usually they are some standard design core with one time programmable ROM. I mentioned it only for complete image, sure they are not for our case, but sales could confuse with soft core.

1. "Genuine" soft core - FPGA - matrix with logic elements and RAM defines connections (rows and columns), also similar CPLD, though different architectures, but near same idea, most difference FLASH (ROM) instead of RAM. Others could be considered hard core.

2. Uncommitted Logic Array, ULA, very similar for FPGA, but instead of RAM, use matrix of metal wires, for example cut by laser. Usually, up to 100% faster than same tech FPGA and have about halved power consumption. And you may already understand, now they used when somebody created successful FPGA design and see market potential to sell few thousands chips. Most known ULAs was in ZX80, ZX81 and Spectrum.

3. Custom chips, I prefer to name they "rendered", because, need physical simulation package to got work.

Exist two types of custom chips:

3a https://en.wikipedia.org/wiki/Standard_cell

Using standard libraries of elements, templates if you wish. So, better than ULA, but worse performance than next type.

3b Full-custom design It is what name suggest - using simulation to make working semiconductor structures. Most important feature - expensive and risky, but if have enough time/money, could make real wonders, like Atari/Commodore chips (except gate array or ULA Gary and Gayle custom chips), or modern CPU SOC if you wish.

https://en.wikipedia.org/wiki/Application-specific_integrate...

It is interesting that the MIPI, PCIe and Serdes columns in the table of device models is "-" for all of them. That is the case for the other Titanium family and nothing is mentioned about Serdes in the datasheet, only in the text description and table for the whole family.

May be, because could implement in FPGA.

The other Efinix chips are still sold as "has serdes" yet have not a single mention of it in the datasheets. At first I thought it was because they're still going through silicon qualification, but it's been 18 months and they're still TBD.

Forgot to add, over that time frame that DID add MIPI documentation so they've got that working.

It's an impressive pile of components on one chip, but the lack of pricing and dev board info is annoying.

Anyone know if Efinix FPGAs have a decent tool chain?

It's a traditional proprietary toolchain (about ~900MiB .tar.gz) that uses Synplify for synthesis and a custom fork of VPR for place and route, IIRC. It's reasonably easy to use and most of the UI flow can be scripted by Python, too, which is pretty nice. It's roughly comparable to something like Lattice Radiant or Lattice Diamond in terms of scope and features, IIRC, not Quartus/Vivado level.

I haven't updated my toolchain in a while so some of this may be out of date.

Small correction, the synthesis tool isn't Synplify.

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