I compared the sizes of several processors[1] including these RISC-V: Glacial, SERV, PicoRV32, VexRiscv and Darkriscv. Compiled to NAND gates the results were 2063, 3595, 34463, 49214 and 50424 gates respectively. Multiply these numbers by 4 to know how many transistors a CMOS implementation would need.
I also implemented them in a bunch of different FPGAs, though that is less relevant here.
Glacial is an 8 bit processor optimized to emulate a 32 bit RISC-V and SERV is a serial implementation of a 32 bit RISC-V. They save transistors at the cost of many clocks per instruction.
There are several projects that implement RISC-V using TTLs but I have not heard of one using individual transistors.