alted

The Hacker Fab [1] project at Carnegie Mellon is creating and publishing guides to building simple fab equipment including photolithography and a sputtering system. For somewhat more complex equipment, I appreciate [2] from the founders of InchFab [3].

But maybe the easiest way to do (very low resolution) photolithography at home is to use dry film photoresist, which is like tape you can stick onto a copper PCB you then expose and etch; a cheap roll is ~$20 from eBay/Amazon.

[1] https://docs.hackerfab.org/home [2] https://dspace.mit.edu/handle/1721.1/93835 [3] https://www.inchfab.com/

Ignoring flexibility and cost/performance, this may be a sign that rapid chip fab turnaround times are possible. These were made by Pragmatic Semiconductor [1], who claim they can make chips within 48 hours and deliver within 4 weeks (likely due to their use of unconventional materials). Traditional silicon fabs, including trailing-edge foundries and TSMC, take 2-9 months. I do wish they'd emphasized this instead of flexibility.

[1] https://www.pragmaticsemi.com/

Has anyone used Perforce Helix for this?

If you're already using it for large file version control for, e.g., gamedev, and don't mind the cost, how well does it work to store all other company documents? I'd assume it has better scalability and permissions management than Nextcloud (not to mention the version control on par with git).

Custom state-of-the-art silicon is ridiculously expensive.

For a minimum 100 wafers = 10k chips, Groq may have paid $100M = $10k/chip purely in amortizing design costs.

Chip design (software + engineer time) and fabrication setup (lithography masks) grow exponentially [1][2] with smaller nodes, e.g., maybe $100M for Groq's current 14nm chips to ~$500M for their planned 4nm tapeout. Once you reach mass production (>>1000 wafers, which have ~150 large chips each), wafers are $10k each. On top of this, it takes ~1 year to design then have prototypes made. (These same issues still exist on older slower nodes, albeit not as bad.)

This could be reduced somewhat if chip design software were cheaper and margins were lower, but maybe 20% of this cost is due to fundamental manufacturing difficulty.

(disclosure: I don't work with recent tech nodes myself; this is my best guess)

[1] https://www.semianalysis.com/p/the-dark-side-of-the-semicond... [2] https://www.extremetech.com/computing/272096-3nm-process-nod...

Pragmatic is very impressive because they're a startup that (a) is building their own chip fab and (b) said fab is much faster and cheaper than existing fabs.

They claim [1] to be able to make chips from a new design in only ~4 weeks compared to the usual 3-6 months required by anyone else, which is huge for R&D. They manage this by using an unusual relatively low-performance process (which is also what allows them to use plastic substrates), but it's arguably a worthwhile tradeoff (in return for slower larger transistors, you get significantly lower equipment cost and lead times). That the chips are flexible is almost an afterthought, I think, albeit a nifty one.

They've also announced efforts [2] toward open-sourcing their PDK, joining the growing movement toward open source chip design.

[1] https://www.pragmaticsemi.com/foundry [2] https://www.pragmaticsemi.com/newsroom/blogs/democratising-i...

Plasticity is interesting because it is maybe the only way to run the Parasolid geometry kernel natively on Linux right now.

Parasolid, the library used to perform the geometric operations (the most difficult and important part of a CAD program) also powers the likes of SolidWorks (the industry standard), NX, and Onshape, and is arguably the best in the world. Its licensing cost is presumably a large part of the Plasticity price.

Excellent question! A sufficiently advanced battery can theoretically beat gasoline.

Any given energy storage technology can store a maximum amount of energy in a fixed volume or mass. Behold one of my favorite plots: [1]

From lowest to highest energy density:

- springs, which use mechanical elastic potential energy, are kinda horrible

- capacitors, which use electric permittivity, aren't great

- next are both batteries and combusted fuels, which both use chemical reactions.

- nuclear gets us another few orders of magnitude

- finally, antimatter (E=mc^2) is a ways beyond that

Both batteries and fuels rely on the energy difference between unreacted molecules, so their theoretical energy density is the same. Well, actually, fuels are burnt to create heat which is converted to energy, and this heat->energy conversion is fundamentally thermodynamically inefficient (only ~tens of percent), whereas batteries are the same sorts of reaction but much more controlled. A sufficiently clever battery, which moves atoms around to react in the right places at the right time, is thus more efficient and thus energy-dense than fuel. However, moving atoms around like this to make a more efficient battery is much more advanced nanotech than what we currently have. But it's theoretically possible.

This is what biology does: us humans are powered by chemical storage (sugar/fat/glucose), which is used more efficiently than current batteries but without combustion. (lithium-ion is ~0.8 MJ/kg, glucose is ~16 MJ/kg, gasoline ~46 MJ/kg)

[1] https://en.wikipedia.org/wiki/Energy_density

A disappointing fact of chip fabrication is the minimum bar is high and expensive.

In other fields, a hobbyist can do wood/metalworking or learn programming or build a robot kit. There's an onramp for people to start learning the skills, which makes a huge ecosystem of gradually improving talent.

But in microfabrication, even though it's the only way to make chips, screens, cameras, inkjets, and LEDs, the minimum equipment cost is millions of dollars. Even worse, it takes even professionals months to fine-tune a manufacturing process to make a new thing.

As a result, R&D is much lower than it could be, and most fabrication is limited to circumstances with a high chance of mass production payoff.

Lower-level teaching resources definitely exist! Here are my favorites:

- The Zero to ASIC course (and Tiny Tapeout) [1] explains transistor circuits and teaches you an open source software stack---and you get a chip physically manufactured! You could make the Nand to Tetris computer in actual silicon (if you can get enough transistors).

- To learn how things are manufactured on silicon wafers, get textbooks on microfabrication. A decent starting point is [2]. There's also a good video series [3] for a quick overview.

- To understand how a single transistor or diode works, get textbooks on "semiconductor devices". A good starting point is the free online [4].

[1] https://www.zerotoasiccourse.com/ https://tinytapeout.com/

[2] "Introduction to Microelectronic Fabrication" by Jaeger

[3] https://siliconrun.com/our-films/silicon-run-1/

[4] "Modern Semiconductor Devices for Integrated Circuits" by Chenming Hu, https://www.chu.berkeley.edu/modern-semiconductor-devices-fo...

Cool project!

Right now y'all look focused on digital logic somewhere between ASICs and FPGAs.

Any plans for custom chiplets? Custom analog layout might be much cheaper if done MPW or Tiny Tapeout style: design a mere ~100x100um area, then bond it to standardized chiplets for control/power.

I believe this is the Voxa Mochii [1].

[1] https://www.mymochii.com/

The probability may actually be much higher: about 12% per decade for a -850mT event; 1.5% for -1700mT [1].

Wikipedia estimates the Carrington was anywhere from -800 to -1750 [2].

[1] "On the probability of occurrence of extreme space weather events", Pete Riley, 2012, doi:10.1029/2011SW000734

[2] https://en.wikipedia.org/wiki/Carrington_Event

A common approach is to use multiple electron beams in parallel ([1] is up to 262144 beams!). This is starting to be used commercially to create the masks for photolithography.

[1] https://www.ims.co.at/en/products/

I do research in a university lab that is also used by a number of companies. People make plenty of transistors, including state-of-the-art research.

However, reasonably sized processors need millions of transistors, and (a) we can't easily make that many at competitive feature sizes, (b) it takes significant time and effort to set up and debug a process, and even more to get high yield. So while it's theoretically possible to make small processors, it's much easier (and, including labor, probably cheaper) to leave that to dedicated fabs. Small prototyping runs (via [1] or similar) are common.

Instead, people use the lab to, e.g., prototype new MEMS devices or test new types of transistors or memory cells. Once the technology is proven, it can be mass-produced elsewhere.

[1] https://www.musesemi.com/

Judging from [1], Sam Zeloof's plan might include using electron beam lithography, which scans an electron beam over a wafer surface, instead of normal photolithography. This can get high resolution (10nm) comparable with EUV, and could theoretically be built out of a hacked scanning electron microscope. Photolithography is the step that limits fabrication size, so e-beam litho allows cheap transistors comparable with state-of-the-art.

The main problem is e-beam litho is extremely slow. It might take ~1 day to do a single photolithography step for a 1x1cm chip, whereas an EUV machine can pattern a 300mm diameter silicon wafer in < 1 minute. (The next problem is making everything reliable. Billions of transistors (a modern CPU) needs a failure rate per transistor of better than 1e-9.)

Maybe that's enough for extremely-low-volume production?

[1] https://mobile.twitter.com/szeloof/status/154993704406717235...

Fun fact: you may know silver (followed by copper) is the metal with the highest electrical conductivity at room temperature, but this is only true in bulk.

When a piece of metal is thinner than 100nm or so, its conductivity increases basically due to electrons hitting the sides. At these thicknesses, obscure metals like ruthenium, rhodium, and iridium can sometimes have higher conductivity than copper and silver. [1]

[1] https://doi.org/10.1063/1.5133671

> the benefits are not as great as I think

It's this one.

You're probably thinking of an electrical insulator solely as a material with low conductivity. Vacuum, air, glass (SiO2) (which is the default insulator in chip manufacturing), and many other insulators all have such negligibly small conductivity it doesn't matter here.

But all insulators have a second relevant property: their permittivity (quantified by a number called the material's "dielectric constant". When this is relevant, people often call the insulator a "dielectric"). When an insulator is between two conductors at different voltages, it forms a capacitor. In wiring this is typically undesired because the capacitor takes energy whenever the conductor voltages change.

In fact, the capacitance of the gate insulator in transistors is what causes most heat dissipation in CPUs! (Which, of course, is a big limit to scaling transistor density right now.) Unfortunately, this is fundamental to how transistors work.

Anyway, for wiring you want the capacitance formed by the insulator to be as small as possible, which you do by choosing a material with the smallest dielectric constant. The dielectric constant of SiO2 glass is about 4 times greater than both air and vacuum, which are about equally good.

But keeping a vacuum in a sealed area on a chip is occasionally used for MEMS devices like accelerometers, gyroscopes, and resonators, which would be slowed down mechanically by air pressure.

A fun one with easy visualization is mechanical engineering statics, in which one calculates how much something deforms from a force (e.g., a bookshelf or bridge sags, a spring stretches, or an elastic tire or sponge or pillow squishes). The standard example is simple beam bending [1].

If you hold a thin beam (say, a ruler or a stiff piece of paper) horizontally in the air by one end, and press down on the free end, it bends from a straight line into a third-order (cubic) polynomial.

To calculate this, one considers the beam as a number of little segments connected to one another. The vertical force on each segment due to the force pressing down is constant over the beam. The first integral of this is the torque ("moment") on each segment. The second integral is the slope of the beam, and the third integral is the actual shape of the bent beam. If you consider it the other way around, the force is the third derivative of the resulting beam shape. This is often visualized in a "shear force and bending moment diagram".

The best part is there's a stupidly simple approximation to calculate how much bending you get from a single force (Hooke's law [2]): the distance the beam moves is proportional to the force (by some constant you can get either with these derivative calculations or by experiment).

[1] https://en.wikipedia.org/wiki/Bending [2] https://en.wikipedia.org/wiki/Hooke%27s_law

MEMS are awesome! Here are some other MEMS devices:

- hard drive read/write heads (the platters are debatable)

- inkjet printer nozzles (this is why making a DIY inkjet printer is nontrivial)

- air pressure sensors (e.g., for car tires)

- precise frequency filters for smartphone wireless communication

- oscillators (https://news.ycombinator.com/item?id=18340693)

- very tiny microphones for smartphones (speakers are harder)

- Digital Micromirror Devices (DMDs): arrays of tiny mirrors used in most projectors

- microfluidics ("lab-on-a-chip" stuff for fast disease testing, DNA sequencing, cell manipulation, etc)

And a couple other semiconductor applications:

- LCD/LED screens (monitors, phones, laptops, etc) (these are made on a glass surface instead of a silicon wafer but use the same basic manufacturing techniques)

- laser diodes (laser pointers, CD / Blu-ray players)

- many quantum computers

The full setup is in the supplementary information (available at the bottom of the main paper website [1]), Figure 7. After this small lens, there are a couple more large lenses before the final camera/sensor, apparently an AVT Proscilica GT1930C (which is not tiny---the full setup would be maybe ~200mm in length).

So basically, yep, this work is just about a better tiny lens; the press article is misleading (the paper [1] is better written). I don't know enough about optics to comment on how it compares to previous work, or how small a full lens + sensor system can currently be.

[1] https://doi.org/10.1038/s41467-021-26443-0

A WiFi/BT/NFC tag system has an antenna, and a radio circuit attached to the antenna.

It's almost possible to inkjet print circuitry with transistors in research applications; see [1]. 20 micrometer resolution is relatively easy, so a WiFi/BT or NFC antenna (~millimeter scale) is very possible. I agree, the tricky bit is making (a) enough transistors to for the radio at (b) sufficiently high frequencies. As in [1], inkjet-printed transistor circuits have at most ~10 transistors as of yet (and NFC chips, with > 512 bit memory, need at least hundreds if not thousands). According to [2], inkjet printed organic transistors are in the range of MHz frequencies; NFC (~13 MHz) may be possible; WiFi (~2.2 GHz) may not be for a while yet.

[1] https://news.ycombinator.com/item?id=24129506 [2] https://doi.org/10.1021/acsnano.6b06041

Nope. Since most manufacturing steps are performed on an entire silicon wafer at once, the cost per chip is cheaper if there are more chips on each wafer. As a result, wafers (for both basic and advanced chips) are filled with rectangular chips packed as tightly as possible (and when designing chips, prices are often talked about in units of "price per area of silicon"). Images from a web search for "semiconductor wafer dicing" illustrate this [1].

[1] https://duckduckgo.com/?t=ffab&q=semiconductor+wafer+dicing&...

And it turns out DIY atomic force microscopes are possible too! (e.g., [1]) It's probably less likely to get all the way to atomic resolution (0.01nm) like a scanning tunneling microscope, but atomic force microscopes can take many types of 1-to-1000nm-scale measurements and are often more practically useful.

[1] https://hackaday.com/2014/04/29/a-diy-atomic-force-microscop...

Previous discussion: https://news.ycombinator.com/item?id=24119102 ("3D Printing Integrated Circuits: What's Possible Now and in the Future?")

Apparently, it's possible to bend existing flat sensors! The backgrinding makes them thin enough to bend. Bending uses high-precision air pressure setups or something. [1]

(This surprised me too, because manufacturing on silicon wafers with non-flat surfaces is very infeasible.)

[1] https://doi.org/10.1117/12.2536025

Yep! This is already done and for exactly this purpose; I believe the common term is "trusted timestamping" [1].

[1] https://en.wikipedia.org/wiki/Trusted_timestamping

Both FIB deposition and its cousin Focused Electron Beam-Induced Deposition (FEBID) are pretty nifty; they can cut/add materials down to maybe 1nm (!) resolution. However, they're extremely slow: they can only affect a single spot at a time and move at maybe only 100nm/s movement, so patterning a useful circuit may take days; it's mostly useful for research work. I don't think I've seen anyone figure out the chemistry to use it to print doped semiconductors, so transistors might not be doable anyway.

Really the only other sub-micrometer 3D printing category right now is two-photon lithography (shine a laser to cure a liquid resin into a solid, like common resin 3D printing), which can generally only use a single, even-more-specialized-than-required-for-inkjet material---almost always an insulating polymer---for an entire structure.

Sure. Heidelberg's recently made [1] some cool tools ("maskless aligners") that can expose a ≈150mm wafer in an hour or so down to ≈500nm resolution, which is very convenient when rapidly iterating through one-off low-resolution designs or something in a research lab (for comparison, electron beam lithography does the same to ≈10nm resolution in maybe a day). It's still part of the whole fabricate-everything-as-2D-layers-on-a-wafer paradigm, though, and has the same limitations (e.g., temperature limits) as standard silicon circuitry made with conventional photolithography.

[1] https://heidelberg-instruments.com/en/#products

The best actually-printed-by-an-inkjet-printer circuits I know of are simple ring oscillators of at most ten transistors or so (e.g., [1]---and they're pretty bad transistors at that), and even the simplest microcontrollers require thousands of transistors.

The paper [2] is a good review of the difficulties. Inkjet printing has at best a ≈20um minimum feature size (vs. 0.01um current transistor sizes), and the material choice is really hard: instead of silicon, you need to make semiconducting inks using funky organic molecules like 6,13‐bis(triisopropylsilylethynyl) pentacene (TIPS‐pentacene). [3] is a good recent paper trying to work around some of these limitations. So everything is still very much in the research phase.

Although inkjet printed circuits won't be anywhere near current silicon circuitry anytime soon if ever (and inkjetting transistors is the best (and kinda the only) method of 3D printing circuits we currently have), the different form factor may be useful. Circuits---even if only a few thousand transistors---could be printed on 3D geometry for interesting microfluidics capabilities, flexible circuits might make good healthcare sensors, and [4] is even studying flexible spacecraft via printed electronics for surprisingly economical space debris removal. And combining all this with 3D printed mechanical parts (via, e.g., the impressive PolyJet [5], which is basically inkjetting layers and lacks only the right materials to print electronics) will be fun.

(as to the source's Air Force Research Lab printed chips, yeah, I can't find further info, either, and agree it was probably sandpapering away most of the spare silicon bulk of an integrated circuit [impressive, useful, but not printing])

[1] https://doi.org/10.1021/acsnano.6b06041 [2] https://doi.org/10.1002/admt.201700063 [3] https://doi.org/10.1038/s41598-017-01391-2 [4] https://www.nasa.gov/feature/brane-craft/ [5] https://www.stratasys.com/polyjet-technology

Soon! But not quite yet.

Like deelowe said, for now, this DragonFly is limited to simple conductors/insulators(dielectrics), which means fancy 3D PCBs (or embedded antennas---see their RFID paper). Transistors, using semiconductors, are significantly trickier.

But special inkjet printers can actually print transistors (e.g., [1])! This is very exciting for the obvious reasons---integrate this with a DragonFly/PolyJet 3D printer/etc. to print complete electronc devices. However, the printers have to use different materials available in ink forms instead of silicon, and even the best are limited to ~20um feature sizes due to ink dispensing difficulties (vs. 0.01um current transistor sizes), so they're still in the research stage.

[1] Grubb et al., "Inkjet Printing of High Performance Transistors with Micron Order Chemically Set Gaps", Nature, https://doi.org/10.1038/s41598-017-01391-2