Sam Zeloof and Jim Keller start a new semiconductor fab
atomicsemi.com
atomicsemi.com
The main problem is e-beam litho is extremely slow. It might take ~1 day to do a single photolithography step for a 1x1cm chip, whereas an EUV machine can pattern a 300mm diameter silicon wafer in < 1 minute. (The next problem is making everything reliable. Billions of transistors (a modern CPU) needs a failure rate per transistor of better than 1e-9.)
Maybe that's enough for extremely-low-volume production?
[1] https://mobile.twitter.com/szeloof/status/154993704406717235...
Not only theoretically. Sam hacked his own scanning electron microscope and did electron beam lithography in 2018.
Now the website claims a fast fab, but leaves it open what that means: fast production of wafers? Or slow production of wafers that run fast?
Interesting. What sort of resolution is that 3D printing though?
> What is the bottleneck in this case?
My guess would be using a single beam? Perhaps it's possible to scale this up to multiple beams working on a die or wafer at a time time?
Which brings up another interesting question. Would this process require the same kind of wafer/substrate as traditional EUV machines? Perhaps using this approach opens up the possibility of using different materials that are easier, cheaper and faster to produce?
Dont't traditional kinds of wafers have to be grown and sliced from exotic/rare materials? If so the additional time to "etch" with this new process might be offset by other factors such as what goes in to preparing the wafer?
Around 50 microns I believe. Not at lithography resolutions obviously, but that's limited by metal powder grain size.
> My guess would be using a single beam?
Electron beams can scan a whole print bed very quickly to heat up the whole top layer [1] which can't be done using lasers. This can be done easily with electrons since they are deflected using magnetic coils, like good old CRT monitors, but this can't be done using lasers because they have to move the mirrors mechanically.
That's why it seemed weird that photolithography would be so much faster, but maybe it's as you say, lasers can be stacked for parallelism to make up for those downsides. Stacked electron beams might interfere with each other because you can't really isolate magnetic fields.
https://www.asml.com/-/media/asml/images/technology/43679-in...
[1] https://www.youtube.com/watch?v=en7hhFJBrAI around 7:30
Everything about this is crazy complex, and the state of the art in any given year is also secret to TSMC and other tiny-feature-size fabs.
But in addition to gradually upping the narrow-bandwidth/phase-coherent illumination frequency every year (which has many problems but continues to see continual progress), they've also long been using techniques to work around the diffraction limit/resolution barrier [1], such as subwavelength metamaterial "hyperlenses" / "superlenses" (previously widely thought to be impossible even in theory) [2][3] and "assist features" and other non-traditional masking elements to pre-compensate for imaging distortions [4]. Plus they fiddle a lot with the chip process to tune it in weird ways to assist with or compensate for the previous issues.
[1] https://en.wikipedia.org/wiki/Diffraction-limited_system
[2] https://en.wikipedia.org/wiki/Superlens#Theory
[3] "Subwavelength-Grating Metamaterial Structures for Silicon Photonic Devices" https://ieeexplore.ieee.org/document/8424820
[4] https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph...
The reality of how this is done is so much more complex than I would have thought: https://www.youtube.com/watch?v=f0gMdGrVteI Traditional techniques such as masks don't work when dealing with xrays.
Edit: linked below, https://www.ims.co.at/en/products/ , says it uses 512x512 beams with a beam field of only 82um. Is that spacing between beams, or width of all the beams together?
The only route to economic viability is absolutely massive beam parallelism inside the tool. But at that scale, there's serious questions about accuracy/reliability. Just one out of hundreds of thousands (or millions) of beams fails for a microsecond and the chip is ruined. This is a problem that is effectively sidestepped for traditional litho -- the masks themselves are created by (slow) e-beam, but mask inspection tools ensure that the masks are perfect before they are actually used to process product wafers.
There are a few dimensions of cost that can be optimized though, right? My understanding is that ASML is making ~10s of these EUV machines per year because of the extreme complexity of many components.
E-beam certainly does provide a bounding limit on how expensive EUV can get, but we're not in danger of hitting that limit anytime soon.
I expect that EUV will become cheaper/more productive per dollar in the medium term, unless ASML starts acting uncomfortably monopolistically (and it's probably in their interest to drive EUV adoption to starve out Nikon and Canon, anyway)
You could imagine chips that are engineered for redundancy / defect resistance, but that would make them a lot less performant so it's highly questionable whether that can be justified by any cost savings on litho.
True, but this is more or less the same process for e-beam and photolithography (as I understand it). I don’t see a fundamental reason why one couldn’t replace one ASML EUV machine with, say, 1000 e-beam machines and run them all in parallel. You would need the e-beam machines to be extremely reliable, but they’re conceptually simple devices and this should be possible.
(With vague ballpark numbers from the Internet, an EUV machine appears to be about 10k times as expensive as a SEM. Building 10k e-beam machines at the same cost as one Alibaba SEM would be an interesting challenge, and there would be factors pushing the price in both directions.)
Fab floorspace is also very expensive, nevermind that's not even close to a realistic price per system (the factory interface alone costs $100k+)
Like the concept of Fast Fashion
While for steady state production, a chip could be produced every couple of hours, no one is going to pay tens of thousands per chip for even a limited production run. If you are doing a one off prototype that justifies an extremely high pricetag, you have long lead times waiting for the chip to go through the various steps.
Honestly you'd be better off just making custom masks.
[1] https://nl.wikipedia.org/wiki/Mapper_Lithography (no English page available)
[2] https://www.asml.com/en/news/press-releases/2019/asml-agrees...
ASML surely charges plenty for their alignment hardware:
https://www.asml.com/en/news/stories/2021/fellow-simon-mathi...
I do think it's a slow market to emerge. They'd need very patient funding. If nothing else, tooling needs to catch up, which is 5+ years.
like if you can do a 7nm or 14nm tier mask maybe that becomes a pivot to a 28nm actual production process, or maybe it makes multipatterning and some of the other advanced-node tricks more accessible at a semi-reasonable cost.
Also (fuzzy memories of semiconductor classes, but) the size doesn’t tell the whole story, right? With photons I’m under the impression that the wavelength of the light is much higher than the feature size, so they have to do funky things with the masks to make it all work out. Playing with interference or whatever. (Someone who knows more about this can feel free to embarrass me, I’m sure it will be educational!)
Electrons are relatively speaking more like the nice little billiards ball thwacking away at the SI that we like to imagine.
They are as long as you keep a close eye on them…
There are now some multi-beam systems.[1]
> We believe our team and lab can build anything. We’ve set up 3D printers, a wide array of microscopes, e-beam writers, general fabrication equipment - and whatever is missing, we’ll just invent along the way.
On the electronics side there is another org nearby (Electronics Yorkshire) where you can hire really expensive inspection equipment (like 3d xray machines etc) by the hour. This is not their core business, but it is a very useful service for startups in aero-space electronics for example. I can't imagine there are no equivalent organisations and university programs in US.
However, reasonably sized processors need millions of transistors, and (a) we can't easily make that many at competitive feature sizes, (b) it takes significant time and effort to set up and debug a process, and even more to get high yield. So while it's theoretically possible to make small processors, it's much easier (and, including labor, probably cheaper) to leave that to dedicated fabs. Small prototyping runs (via [1] or similar) are common.
Instead, people use the lab to, e.g., prototype new MEMS devices or test new types of transistors or memory cells. Once the technology is proven, it can be mass-produced elsewhere.
This works well for the uses cases you describe: dedicated inspection equipment or very niche small scale nano fabrication needed. But making a a fully working VLSI CMOS process needs much higher complexity and many more different process steps and equipment.
Which brings me to the second point: - Research labs typically don't care much about yield: they need sufficient amount of working devices to measure and show things are possible and publish about it, but they do not need to bring it up to reliably reproducible results. However when you make an ASIC with millions to billons of transistors and wires, you typically depend on ALL vias and ALL transistors working, not just 80-90% of them, to get a functional chip. This is a lot of hard and dedicated work, in a way it's an art, black magic almost to most: very few people and companies have the expertise to pull this off. It's not a big exaggeration to say only TSMC can do this really well. Just look at how much even Intel is struggling to get their next node out (it's been how many years of Tick Tock Tock Tock Tock.. now?)
In the US there's a consortium of fabrication centers[^1], but even if a uni has a clean room, I think a lot of custom designs often go through China because it's less hassle.
Due to the practical limitations on "direct" reticle size for maskless lithography, you already need reticle stitching for matching any modern (think, this century) mask-based photolithography VLSI capabilities, and thankfully most maskless reticle stitching tactics can be scaled to an entire wafer. [0] Some tactics likely need mechanical re-positioning of the write head to different parts of the wafer due to Etendue limitations of commercially practical optics (keeping sharp focus across the entire optically reachable area, within which they rapidly write individual reticles at reticles-per-second rates IIUC usually somewhere in the audible range), but the same mechanism that's used to track alignment of the lithography layer to those of previous steps, can typically be adapted to work across mechanical scanning within exposure of the same lithography layer.
While wafer-scale integration naturally needs defect-compensation, modern micro-channel liquid/phase-change cooling can already handle heat removal at desktop Zen3 chiplet power densities without needing a heat spreader to thin the power density out.
Tactics like feeding in the liquid parallel to the chip, and letting it boil on the chip-side of the structure, to then let the vapor escape normal to the chip (if it's flat, this would be vertically upwards), can scale to very large areas because you can put occasional liquid feed pipes in the vapor-space that are thick enough to not cause excessive pressure loss, and thus scale from having to pass the liquid sideways across the entire chip to something with less flow resistance (pressure drop) for the escaping vapor.
3D printing can manufacture those intricate structures that allow exceeding areal power density limits of nucleate boiling (which are around 10~30 W/cm² for chemically/environmentally tame hydrocarbons (e.g. Pentane, boiling comfortably at 1bar/2bar/5bar at, respectively, 36°C/58°C/92°C, low toxicity but more flammable than gasoline), and around 100 W/cm² for water (sadly, 120°C surface temperature isn't practical for silicon CPUs)).
Wafer-scale processors are just extremely capable compared to normal reticle-limited ones, see e.g. how Cerebras manages to run fluid dynamics simulations for things like iirc helicopters at/above realtime speeds, enabling predictive control in aerodynamically unstable situations.
Allowing manufacture of processors not limited to special reticle-border-crossing wires is, IMO, quite ground-breaking. Imagine things like hex or triangle grid mesh networks on the chip, and just overall a far more homogenous mesh topology just about flexible enough to route around the defects, possibly using just the normal required back-pressure routing to deal with the congestion-hotspot from needing to divert around a disabled cell (and do so without the greater surroundings needing to even be aware of that cell being disabled). [At worst a disabled area would need to be turned into a rectangle to make adaptive Manhattan routing work. The software would need to be taught to deal with holes in the physical-location-based address space, but many algorithms are inherently tolerant enough to deliver proper useful results even with their data grid having holes/crystal defects, and a physically homogenous grid of cores (should, IMO) fit(s) those better than one less-homogenous that can fully mask deactivated cores (like Cerebras's device).]
And beyond wafer-scale processors, analog VLSI processors (they could be manufactured using traditional photolithography) are awesome. There are just two major obstacles in the way of utilizing them:
1) they don't allow much flexibility in even simple operating parameter tuning (let alone larger FPGA-like reconfiguration) to use a generic chip in many situations/different devices. Thus they need a low practical MOQ for broad utilization.
2) due to difficulty with simulating/modeling the entire dynamic system they operate/control, substantial iterative experimental tuning of the hard-coded (though literally the shapes of the devices manufactured in the integrated circuit) parameters will be necessary during product development. Mask-less lithography is inherently able to manufacture down to single-digit MOQs (only really limited by stochastic yield/binning and multi-step-process lead times). [It's trivial to sample the hard-coded tuning parameter space, via simulating behavior differences, and then sampling finely enough to not miss the perfect range of parameter values as a result of manufacturing yield/rejects poking holes into the sampling grid.]
I believe there are substantial opportunities in electronic power converters, due to the frequencies unlocked by recent advances in [high-frequency-capable] SiC and GaN power transistors. And how multi-MHz switching shrinks the size of capacitors/inductors/transformers, in exchange for demanding extremely rapid control (and worse, often limiting the current of a single module due to speed-of-light effects, which implies many individual controller chips).
For reference, here's a list of commonly-encountered electronic power converters that typically aren't made in the quantities needed to make traditional analog/mixed ASICs economically feasible: "computer power supply", "high-efficiency electronic motor controller" (which are just fancy variable power supplies commanded by a controller that translates input commands and possibly sensor feedback into drive voltages), "solar panel to power grid adapter" (regardless of whether the grid is a normal AC grid needing it to be an inverter, or if it's a DC grid needing it to only adapt the voltage), "battery charger" (essentially all types, except if the voltage matching is done by an external device like how electric cars with DC fast charging only request the desired voltage from the stationary "charger" (itself "just" a variable power supply)), etc.
[0]: [With DLP chips, you get single-exposure pixel counts on the same scale as contemporary TFT (I e., active, large-panel) LCDs (the kind used in flat screen computer monitors and TVs; this stems from a large (if not the largest) market for DLP technology being projectors/beamers), and electron-beam approaches run into issues with deflection mechanism linearity (i.e., pixel spacing uniformity between center and borders) in the 1000~100000 (1k~100k) linear pixels (width, in the fast axis).]
Sam Zeloof is known from his YouTube channel[1] where he shows how to build microprocessors in detail.
I hope that this step is the first of many to build an efficient processor with fresh ideas and innovation.
The Alpha made all of that moot because in one fell stroke it increased the amount of RAM that could be addressed directly to the point where the whole thing could happen in memory without any cluster communications overhead. It was still an expensive machine but it cost a fraction of the setup that it replaced, and performed really very well. A nice example of how vertical scaling can be a very viable option. The 64 bit file system also allowed for much larger files, which helped the project in different ways.
One downside was that spare hardware was difficult to obtain but the system was built like a tank and ran for many years until there were many other suppliers of 64 bit systems.
It was way ahead of the anything else in the 'affordable' range of computers. Though it still cost as much as a nice car fully decked out, especially the RAM was quite expensive.
Azul later realized some of these things on Java. Building a virtual machine and even language to take advantage of that from the ground up would have been cool.
The processor's firmware (PALCode) was essentially a single-tenant hypervisor, and the OS kernel made upcalls to the firmware in order to perform any privileged instructions. Had the architecture survived longer, this would have been handy for virtualization. Modern OS kernels have special cases for upcalls when running on top of hypervisors in order to avoid some of the overhead of the trap-and-emulate code in the hypervisor.
The designers were brutal in only including instructions that could show a performance improvement in simulations. The first versions of the processor didn't have single byte loads or stores, presuming that the standard library string functions would load and store 64-bit words at a time and perform any necessary bit manipulations in registers. They later relented and included an instruction set extension for single-byte operations.
They were also famously brutal in their memory model, leaving as much leeway as possible for hardware to re-order operations. As long as you're correctly using mutexes to protect shared state, the mutex acquisition and releasing code will properly synchronize all of your memory operations. However, if you're implementing lockfree data structures, the Alpha is particularly liberal in its read ordering, and you need read fences on the reader side of lockfree structures, which is unusual. Experience has shown that for most code, the potential performance improvements aren't very significant, especially considering the increased potential for concurrency bugs.
I'm pretty sure that if you had dropped that from the 10th floor of a random office building you'd be fined for damage to the pavement but that machine would have still worked ;) It also took two people to lift it.
And now your average phone has more CPU power and more storage...
Times, they are a changing...
I not a architect and don't know enough about the topic, but I thought that might be something interesting for RISC-V. Love to read about the advantages and disadvantages of that.
In the absence of a read fence, you can speculate the address of a second load, execute this second load in parallel with a first load, and ignore a cache invalidation (or just not wait until you can rule out an asynchronously transmitted one) hitting the second load so long as the address (computed from the first load's data) was correctly predicted. It hits even harder when the predicted address was a cache hit and the first load experienced a cache miss, because now you can speculate execution using the second load's data (delivered from the cache) and retain/confirm/retire the results of the speculated computation as soon as the first load's data returns and the computation of the second load's address confirms the speculated one.
An example is read-only access to data structures with pointer chasing while a different core performs copying garbage collection. Because the data is (semantically) read-only, the old copy and the new copy are both equally valid, and as long as you don't accidentally read the new space before the copy was written into it, you can pointer-chase freely through these structures reading the next e.g. linked-list entry from either the old or the new place (if you speculate correctly).
Critically, this could get by with invalidating only cached data for the copy target range, ensuring readers don't get the uninitialized data, without invalidating their cache of the copy source range. Of course that would require sufficiently targeted invalidation.
Other cases like e.g. typical union-find / disjoint-set datastructures work just fine with standard fence-free Alpha memory accesses, at the slight cost of `union` operations not coherently affecting outcomes of `find` operations. That's often not a problem, though, as parallel applications already have to cope with the `union` racing the "subsequent" `find` operations (and ending up with the `union` happening last).
Long story short if I had money that would be relevant in this context I would invest really hard into Tenstorrent.
Investing time to listen to the guy seems to be not worse.
1a. https://www.youtube.com/watch?v=Nb2tebYAaOA
1b. https://www.youtube.com/watch?v=G4hL5Om4IJ4
Some former AMD employees started it.
From Jim himself:
> IC: A few people consider you 'The Father of Zen', do you think you’d scribe to that position? Or should that go to somebody else?
> JK: Perhaps one of the uncles. There were a lot of really great people on Zen. There was a methodology team that was worldwide, the SoC team was partly in Austin and partly in India, the floating-point cache was done in Colorado, the core execution front end was in Austin, the Arm front end was in Sunnyvale, and we had good technical leaders. I was in daily communication for a while with Suzanne Plummer and Steve Hale, who kind of built the front end of the Zen core, and the Colorado team. It was really good people. Mike Clark's a great architect, so we had a lot of fun, and success. Success has a lot of authors - failure has one. So that was a success. Then some teams stepped up - we moved Excavator to the Boston team, where they took over finishing the design and the physical stuff, Harry Fair and his guys did a great job on that. So there were some fairly stressful organizational changes that we did, going through that. The team all came together, so I think there was a lot of camaraderie in it. So I won't claim to be the ‘father’ - I was brought in, you know, as the instigator and the chief nudge, but part architect part transformational leader. That was fun.
https://www.anandtech.com/show/16762/an-anandtech-interview-...
If he says it was a team effort, especially if he’s speaking clearly about the different aspects and who was responsible for them, I wouldn’t disagree with him. He would know after all.
Its human nature to pick out heros, say they did everything by themselves and idolize them. That doesn't mean it's real. It's just a story you're telling yourself.
I've never heard about the people mentioned here, and I don't know anything about semiconductor manufacturing. Except that it's one of the absolute most complicated things humans have ever attempted and there's no way a single person could be the creator of an entire modern processor architecture. So I've been reading through this thread kind of surprised to see people saying this one person did so. But your comment made me realize it's just typical hero worship.
Note: this doesn't belittle the work of anyone. Schumacher is an amazing driver, one of the best in the world. But saying he is responsible for winning formula one races belittles the work of the other people involved, engineers at the top of their game just as much as he is, and yet faceless to most people. He could be exactly the driver he is, or even a hundred times better, and without equally talented engineers behind him he'd still finish in last place. So did he win the races, or did they? Obviously, the answer is that they won together.
Just because they arent celebrities it doesnt mean that they do not exist
https://en.wikipedia.org/wiki/AMD_Platform_Security_Processo...
His greatest hits: DEC Alpha, AMD K7 (Thunderbird/Athlon), AMD K8 (Athlon 64), Apple A5, AMD Zen... probably others I'm forgetting.
Like god damn can someone else in the industry have some ideas of their own please, lol /s
And again not that other people aren't involved either, in particular Mike Clark was really the guy who executed Zen development, but Keller was there at least as an advisor for a lot of the early development. He's one of Zen's uncles, Clark is the father. https://www.youtube.com/watch?v=3vyNzgOP5yw
I think it also says a lot that he completely fucking bailed from Intel after only being there a couple months... I think he saw they just weren't ready/willing to execute well and his time would be wasted there. He's the wandering silicon samurai who drops some golden nuggets of advice and wanders off into the sunset, not a babysitter while you purge middle-managers playing office politics.
(He left due to a "family situation" and while I have no doubt that it was real... I also think he probably might have stayed if Intel wasn't a complete dumpster fire too.)
I was disappointed when Apple switched to x86 instead, and a few years later, Apple acquired P.A. Semi, which I believe became the bulk of Apple's mobile processor team.
If rumor is to be believed, it really is too bad that Ken Olsen refused to drop margins and increase volume on the Alpha in order to create a scaled down version for Apple back when Apple was looking to leave the m68k architecture.
even if he's not the determining factor of success - as he clearly said it's a team effort - he's very likely a safe bet, and a good canary, a good advisor (not a yes-man).
https://www.youtube.com/watch?v=3vyNzgOP5yw
Probably the most interesting nugget is that Zen2 was actually considered a tweak internally and not a full uarch revision, while Zen3 is actually the clean-sheet revision. But it's just a good summary of the general tone and tempo of CPU development I think.
How would one go about doing this?
I would happily accept a bet (e.g. $100 bucks or a nice bottle of whiskey) from you (or anyone) that atomicsemi is successful. I will just bet against it because I am skeptical that a new company is successful in a capital intensive segment.
It is probably slightly insulting, foolish, and arrogant to bet against the famous Jim Killer on a website dedicated to startups. This should not be a dig against Sam and Jim Killer. I guess that will try something truly innovative. But if I look a the past, the odds seem to be stacked against them.
And Tenstorrent I still see as a risky bet, but in my mind it's very +EV.
Everything is ML nowadays and we still use very naive approach driven by what hardware was available at hand.
Different spaces, different people, but I'm going to sit back and observe I think. I'm just kind of done being excited by people announcing the partnerships, once the partnership bears fruit I will have a look and then decide if I'm excited.
I know about the history of semiconductors in the SV but so much has changed in the world since then.
Does being located here these days actually being practical advantages to running that kind of business, like having a greater talent pool? Is it more of a branding/identity thing?
I'm also not sure if we will really see a manufacturing renaissance but if we do I bet it will go hand in hand with a lowering in environmental standards.
So it remains expensive and still a great place to start.
(I believe. My 2cents)
Great to see an apparently US-based fab opening though (I'm not from the US, but anything not based in China seems to be good for the industry)
https://atomicsemi.com/careers/?ashby_jid=c991fb4d-e634-42f2...
That can actually successfully perform that work. All for 100k-170k in SV. The Lab tech again has a very high skill requirement and quite low pay:
https://atomicsemi.com/careers/?ashby_jid=bb2112f2-914a-4ee0...
In all honesty I think working for this would be fun but also insanely stressful and note worth if for the employees.
Anyone with that XP concretely applying those skills at most commercial fabs is easily creating millions of dollars of value (as a portion attributable to their contribution to the overall fab's value creation); if at all, it's absolutely insane that they get compensated so little on average.
That could well turn out to exceed the regular wages. Besides, working with a small world-class team is a great learning experience and big reward in itself.
I don't know anything about wages in SF but the requirements are niche to say the least, and all wrapped in "2+ years of industry experience". Good luck to them.
I think he’s got enough of a twitter following that he might be able to attract a crew who has the same recreational attitude towards semiconductor fabrication.
Question though - if your salary was at the low end of that range why does this seem too low? What would seem like enough? Im assuming those jobs were in related fields and that you would have a stronger impression of what would be attractive for a person in that position than I would
I don't have actual data backing me up. It seems low to me because I have gotten the following impressions, some of which may be wrong:
* San Francisco is one of the most expensive cities in the world.
* Startups in Silicon Valley routinely receive tens of millions of dollars in funding despite having questionable business plans, conflicts of interest, and mentally-unstable founders.
* Even SWEs who just graduated from college can get upwards of $150k/year at major tech companies, even if they spend most of their time just copying and pasting from Stack Overflow.
* Good electronics engineers are rarer than good SWEs. Good electronics engineers who can also design high-precision machines are extremely rare, and the ones with semiconductor experience are probably earning big salaries at large companies.
* Hardware development is much more expensive than software development. In particular, hardware design errors can be much more expensive to fix.
* Getting a new manufacturing process up and running is a lengthy and capital-intensive task. Creating a totally new kind of manufacturing process to "disrupt" an established, competitive industry could charitably be described as "high-risk".
* Hardware startups rarely make it big, and the ones that do seem to be associated with trendy software stuff like crypto, AI, and quantum computing.
To summarize, a startup that's going to be spending a lot of money on hardware development in a very expensive city wants an experienced engineer with a specific and unusually-large skillset, and they're offering a salary that barely competes with an entry-level SWE job along with some high-risk stock options.
As another comment said, it sounds like they want someone who will treat this as more of a hobby than a job. Which is fine, but I feel like the proper job title for that is "independently-wealthy cofounder", not "hardware engineer". (Alternately, I've heard that highly-specific job offers can be used as an excuse to get an H-1B visa -- maybe they're looking to hire someone from Taiwan. Or maybe I'm just being cynical.)
170k is a pretty normal senior SWE salary for Bay Area startups or even FAANGS. The crazy TCs come from equity and, to a lesser extent, bonuses.
If this leads to a startup with a parking lot full of Porsches, well, that's not such a great sign, having BTDT. You want lean and hungry people at a lean and hungry company. People with something at stake -- if only their pride -- and something to prove. Not people who were "10x performers" at their former startup and are now, post-exit, convinced of their own intellectual immortality.
IMO they're better off hiring engineers like everybody else does, by paying market compensation.
There is a very interesting initiative in Japan: https://www.minimalfab.com
I wonder whether this is similar to what Sam Zeloof has in mind? I went through the website, job postings, twitter threads etc. but I am not sure what they are actually trying to do.
There used to be a crazy startup with a simiilar business approach in mind that tried to manufacture devices in small spheres of silicon: ballsemi. Their website seems to be defunct, but there is an article here:
It'd be fabulous if atomic went the Open PDK route like Skywater 130nm: https://skywater-pdk.readthedocs.io/en/main/ but even a setup with a 'here's the fab price list click here to pay us $x'000k and sign our NDA to get access' would be a big step forward. Combined with reduced manufacturing costs it would make it far easier for smaller players to experiment with custom silicon.
Yeah, but the business model of providing accessible standard CMOS technology would not really require building new tools, wouldn't it? I think the appeal would be in being able to build devices in highly customized technology.This would require fast learning cycles at low cost. Not really something a MPW helps with.
I mention skywater 130nm not because of the MPW program but because it's an open PDK, you can just download it and go use it, without needing to pay anything or sign any legal agreements. Maybe Atomic would go the same way?
https://www.industrie-techno.com/mediatheque/6/4/7/000004746...
Slide 17 is a comparison of the concept to a large fab.
(He seems to have had access to the kind of garage and equipment other engineering kids can only dream of though. I know someone who really wanted to do the same thing a few years earlier, who had the knowledge but couldn't get themselves a suitable place and budget to do it.)
Jim is, from what I can tell, an extremely good leader, and Sam appears to have limitless energy for experimentation and limitless passion for this field.
I hope they not only succeed with their fab, but that in some way they can make at-home (or otherwise small-scale) prototype chip manufacturing easier, less expensive, and with fewer barriers to entry. Given the physics involved I don't know how much they can succeed at that, and I don't even know if that is a goal of theirs, but it would be nice to see, certainly.
These folks deserve success and I'm sure they will attain it, no matter what their goals are, if their fate is in their own hands.
In a similar vein:
> But I do note that if you run the structure through SciFinder, it comes out with a most unexpected icon that indicates a commercial supplier. That would be the Hangzhou Sage Chemical Company. They offer it in 100g, 500g, and 1 kilo amounts, which is interesting, because I don't think a kilo of dioxygen difluoride has ever existed.
https://www.science.org/content/blog-post/things-i-won-t-wor...
I doubt he's talking about building a company that sources their machinery/parts/gadgets directly from places like Alibaba, Taobao, etc...
> If you wanna do high volume production, good yield, standard process, etc then it’s 12bn$
You sure can if all you want to print is one 100mm wafer per month.
Multi-beam tools that can reduce that to a wafer (or reticle) every few hours are real fscking expensive.
Doesn't stay still for very long.
The guy has a career older than most people on this forum.
This tweet alludes to Sam being associated with Atomic Semi https://twitter.com/szeloof/status/1628528981430657026
And this twitter thread mentioned in the comments makes no mention of it: https://mobile.twitter.com/szeloof/status/154993704406717235... (Ctrl + F "Jim" or "Atomic" gets me zero hits)
Maybe I am dense, but where is Atomic Semi saying that it is being started by Sam Zeloof and Jim Keller, especially if the title is saying that (which I thought titles weren't supposed to be editorialized)?
I would hope that there is more concrete evidence (especially if that is the Headline!)
> retweeted this post from Sam: https://twitter.com/szeloof/status/1628528981430657026
Yeah I made mention of that. So it alludes to Sam being involved with it.
https://www.wired.com/story/22-year-old-builds-chips-parents...
Is Grayskull being shipped in quantity?
When can we expect Wormhole?
https://pitchbook.com/newsletter/openai-to-back-keller-and-z...
Very similar goals, including fab suitable for low-NRE open source hardware design iterations, but grander vision: making more of the hardware tools as well instead of purchasing them, building a stack that is not silicon-specific, extensive use of physics simulation and feedback to design specialised toolchains. That is partly because bootstrap finance requires inventing cheaper tooling than is available on the market, not just cheaper lithography.
Atomic Semi will almost certainly get their faster due to funding, better network, more pragmatism, track record of the people involved, and location. But friend's thing might go further into advanced and novel capabilities, eventually, if they continue with it.
Interestingly, their original goal was to stimulate a culture of open source hardware at the lower levels by providing a service to fabricate new designs at low cost, the way that has already happened with software, i.e. anyone can learn it in their bedroom and take it as far as their skills permit, causing a significant change of culture and knowledge sharing. That goal doesn't seem to be needed any more because of the Efabless-Skywater-Google collaboration making hobby-level ASIC fabrication available for free, and the rapid increase in available open source hardware design tools at steadily higher quality. And things like Atomic Semi emerging. The culture has already changed.
Jim Keller is still CEO of Tenstorrent right? If so then is this Jim vertically integrating in a way? I don't know much about Grayskull tbh, but this would make sense.
Well, there's comma.ai [0], which is very rare from a company I have seen on what they have as a small startup.
Something that managed to be more safer than Tesla FSD (Fools Self Driving), and not some vapourware like Zoox, Drive.ai, Lyft, and Uber's self driving ambitions which all have amounted to very large costly contraptions that went on the road to no-where.
Is this the same entity? Any info on IPO?