solarexplorer

Here is another one: https://en.wikipedia.org/wiki/Sam_(text_editor)

I have used both editors quite a bit and did like both of them.

What you describe sounds counter-intuitive. And the paper you cite seems to suggest an ISA extension to increase the number architected (!) registers. That is something very different. It makes most sense in VLIW architectures, like the ones described in the paper. Architectures like x86 do hardware register renaming (or similar techniques, there are several) to be able to exploit as much instruction level parallelism as possible. That is why I find you claim hard to believe. VLIW architectures traditionally provide huge register sets and make less use of transparent register renaming etc, that part is either explicit in the ISA or completely left to the compiler. These are very different animals than our good old x86...

Have they? Netflix, Spotify, Kindle, ...

I don't know. I use a lot of Swift and C++ and while both are OK languages there is an absurd amount of complexity in these languages that doesn't seem to serve any real purpose. Just a lot of foot traps, really. Coming back to Plan9 from that world is a breeze, the simplicity is like a therapy for me. So enjoyable.

If "modern" means complex, I don't think it fits Plan9.

> Propane gas tanks became registered products

I still remember the two gentlemen in their black, faux leather jackets who rang our doorbell and demanded to see our dinghy. (dinghies where registered products too) We showed them our dinghy, they said thank you and left.

Probably someone fled over the Baltic sea to Denmark in a dinghy. So the secret police went from door to door until they found someone who could no longer show it to them...

This was in the late 80s.

Yes, I think the conclusion was that it did improve performance on binaries that were not compiled with optimizations, but didn't generate enough gains on optimized binaries to set of the cost of re-compilation.

https://dl.acm.org/doi/10.1145/358438.349303

(this is not about x86 but PA-RISC, but the conclusions would likely be very similar...)

That they will invest 10$ in OpenAI for each W of NVIDIA chips that is deployed? EDIT: In steps of 1GW it seems.

Yes, gentrification is a thing around here too, but I also lived in the outskirts of the city and you don't need a car there either. They also have all the essentials. The fancy restaurants and theaters are 30min metro/bus away, but otherwise it is fine too. A car is a luxury in those quarters too.

Completely agree that the presence of bikes and scooters on the sidewalk is annoying and dangerous. The city changed the rules a few months ago and now there is a 500€ fine if you use them on the sidewalk. That fixed the problem. They have to use the street or one of the many bike lanes.

No idea how it is in Paris, but there are places where living happily in a city without owning a car is perfectly possible, even if you have small kids.

It really depends on the city/quarter where you live. I live in the center of Barcelona and had no problems with two small kids at all. Supermarkets, real farmer's markets, hospitals, pharmacies, schools, etc are all within 10min walking distance. I work from home, but I could walk to the office it I wanted to. I don't have to leave the city at all.

Eventually I gave in and bought a car, not because it was necessary but rather to leave the city on weekends and get closer to nature.

> They are the gatekeeper to one thing: their own app store.

They also control the OS and don't allow side-loading or other app stores (without putting absurd obstacles in the way) So in the end they completely control the devices they sell.

Good call, thanks for clarifying!

I would assume that "lightweight" in this case means that they share a single Linux kernel. Or that there is an emulation layer that maps the Linux Kernel API to macOS. In any case, I don't think that they are running a Linux kernel per container.

This is not a good article and the content doesn't support the claim in the title. It talks about memory latency and how it negatively affects instruction level parallelism, but doesn't offer any solution or advice, except for offering their own (payed) service...

Yes, in theory you can pause at any point, but in practice it is not that easy to stop. I remember not hearing the boarding call and losing a flight while reading La fiesta del chivo…

More details here: https://archive.ph/vabvA (Spanish)

There is also the first object in space. But this was arguably no commercial launch.

https://en.wikipedia.org/wiki/MW_18014

I don't have any numbers, but I think this is still pretty common. On iOS for example Alamofire which is a popular network stack, still offers this as a feature. I think the use case is a bit different for apps and web sites, especially for closed ecosystems like Apple's where reverse engineering is not as easy/straightforward.

https://github.com/Alamofire/Alamofire

IIRC it also introduced index based addressing. Before that, people just wrote self modifying code to index arrays...

Maybe some kind of snapshot feature, where you can just load an snapshot of the already initialized state?

If I understand correctly, the AI is only choosing the optimization passes and their relative order. Each individual optimization step would still be designed and verified manually, and maybe even proven to be correct mathematically.

Very nice! Thanks for sharing! Getting to the point where you can run other people’s code is a great achievement!

I have one question: Did you really implement this in Python? Why not C++ or Rust?

MIPS for example has this. It has `addu` for normal integer addition that does not trap and `add` if you want to trap on overflows.

IIRC you don‘t have to do 16 trips in four months. If do fewer trips, you have to pay 10€ once (or 20€ for the mid range trips). That is still a considerable discount.

We do have these architectures already in the embedded space and as DSPs. I suppose, they would be interesting for supercomputers as well. But for general purpose CPUs they would be a difficult sell. Since the memory size and latency would be part of the ISA, binaries could not run unchanged on different memory configurations, you would need another software layer to take care of that. Context switching and memory mapping would also need some rethinking. Of course, all of this can be solved, but it would make adoption more difficult.

And last not least, unknown memory latency is not the only source of problems, branch (mis)predictions are another. And they have the same remedies as cache misses: multithreading and speculative execution.

So if you wanted to get rid of branch prediction as well, you could come up with something like the CRAY-1.

In the same section the part about the SiFive optimization is also misleading. The goal of the optimization is obviously to avoid interrupting the instruction fetch. But he makes it sound like the goal was to reduce instruction count by fusing two instructions to get a single monster op with five (!) register operands. That just doesn't make sense.

I like to remap Caps Lock to Control to get a similar layout as the old Sun keyboards. It also makes pressing the Control key a lot easier.

I wonder if RISC-V has a standard way to handle these custom instructions. Is there an easy way to trap these custom instructions and emulate them in software, or is there something like CPUID, or do you just don't distribute the binaries with the custom instructions?

Or you could just use React Native and push new features directly to the app...

I have seen this a lot, am I the only one who thinks that this is ugly?

Crafting a protocol after the fact to match some class' interface (and then put an empty extension) seems just wrong.

I very much prefer to pass simple types around. (like two closures in this case) You don't need to remember any protocol name and don't need to define a ton of mock objects.

To check with your passport/id card that this is your QR code and not someone else’s…