339 karma · joined November 26, 2012
I would assume if that law passed the simplest compliance would just be to charge subscriptions and stop selling games directly. It seems like doing that would comply with that law without requiring much to change?
I suppose what winds up where is up to the memory controller but (for DDR5) in each BL16 transaction beat you're usually getting 32 bits of data value and 8 bits of ECC (per sub channel). Those ECC bits are usually called check bits CB[7:0] and they accompany the data bits DQ[31:0] .
If you're talking about transactions for LPDDR things are a bit different there, though as that has to be transmitted inband with your data
There's a pretty good set of diagrams and descriptions of the faults in this paper https://dl.acm.org/doi/10.1145/3725843.3756089.
Also to the parent: there's an updated public paper on DDR4 era fault observations https://ieeexplore.ieee.org/document/10071066
The overall CPU Market Share number also includes both IoT and SoC numbers which are not included in the other numbers and in which Intel's shipments have declined substantially while AMDs SoC products (including game consoles) are making up a large number. This is what's responsible for the disparity.
They also added that the data was distributed with a helpful clarifying note the news articles are mostly omitting:
* Please keep in mind that due to the inventory corrections taking place, that the statistics and share movements reported here in the past few quarters -- and likely for the first half of 2023 -- are more reflective of the suppliers differing in the depth and timing of their inventory corrections, rather than indicating sales-out share of the PC market, which is something we probably won't know with any accuracy until late in 2023. *
Measure Response: Determine what an adversary nation does in response to the violation (what resources are scrambled, where do they come from etc)
Messaging: All the permutations of two sets of government folks trying to send a message the pair mutually understand re: defense etc
Tie up resources: Low cost provocation may divert higher cost resources and tie them up for a longer period of time since its a dwelling threat
Acquire signal information: Use sensors and measurement systems outside of the threat to measure the locations and signatures of tracking systems deployed to assess and monitor the threat
Deploy lightweight physical payloads: dust something of interest over an area etc
One pretty consistent way to see this is to ask for various very simple designs like a n-bit adder, it will almost always do something logically incorrect or syntactically incorrect with the carry in or carry out
For those who do find themselves bothered by this kind of thing, these projects are almost always a few layers deep on what they're actually researching. I would assume this is more fun demo with a potential economic application in large scale roasting but that the research value (and intern training value) are in the general research area of broad solar concentrator R&D. If you look at the publication history for the folks involved you'll see a lot of papers on molten salt solar concentrators (materials, plant design, physics of etc).
Sandia does a lot of really interesting and valuable research (across all the sites but NM and CA in particular).
What I mean is just that the announcement seems to be more of a branding exercise than a fundamental shift in what's included in a degree program. If you look at what they describe as the curriculum for example: undergrad: https://engineering.purdue.edu/semiconductors/degrees grad: https://engineering.purdue.edu/online/programs/masters-degre... These types of courses are very common among most curriculum I've seen as are many of the things they're offering (e.g. have a design fabricated something universities have done through MOSIS for quite some time or time in a university research fab which many schools have also had.
The positioning in the article seems to be highlighting the growing need for fab-type engineers though and I think that's not quite a match for what's on offer here. If you want to do very fundamental semiconductor device work like designing new device types or fabrication techniques there are some jobs in this but they do typically require a graduate education likely a PhD and are much more limited. If the construction of new fabs is what they are saying drives the need for a bigger wider program what is actually needed isn't device designers and engineers its tool owners, process managers, technicians/operators etc.
In semiconductors I'd say things are divided kind of between 1. Front End Design (Digital+Architecture and Analog) where the better and more plentiful jobs are (with more in the digital side) 2. Backend (timing closure, placement and routing, final simulations etc) 3. Process Design <-- this is where you're doing everything from figuring out how to manufacture a device you designed, implementing new and novel structures, doing a lot more 'chemical' type work potentially for things like interconnects etc. There are far fewer of these jobs 4. Manufacturing <-- running the process of operating a fab, making sure things are fast, repeatable and smooth, testing the output products from process stages to chip sort and test etc. This is much more full of technicians and some supervising engineers.
If I was trying to make an analogy to more software like roles, the manufacturing + backend folks are people running the build process, the process designers are a small library designing team and the frontend design teams are the bulk of the folks using all of the above to implement chip designs. You can get into the analog and digital design side with an EE masters in VLSI from most programs.
The programs Purdue offers can definitely get you into any of these types of role depending on what you do or are interested in, but what they're talking about in this writeup doesn't seem like a fundamental shift. If the goal was something more industry focused I could see perhaps creating a bunch of new courses or co-ops focusing on more industrial concerns (DFT/DFM, process management, simulating for non-idealities etc). I don't see the curriculum being wildly different in a way that things wouldn't slot into the more traditional roles at all. I don't think this is a bad thing, I just think this announcement is a bit more on the marketing side letting people know this is available.
As far as the provide truly novel techniques, I think there are plenty of those being designed for various special purposes in universities. Sometimes these designs lead to interesting industrial applications but the thing that's usually an issue is that industry focus is on predictable, low cost and high yield. The type of research industry will do typically enables generational jumps in density or power improvements etc but until its really necessary they'll wait to adopt highly novel academic research and then spend time figuring out how to make things manufacturable.
The reality of getting a job in semicondutors though is most likely you're going to do something design/verification related, process work will come to you from your fabricator in the form of a PDK (process development kit) which will have all the parameters of the process and rules for manufacturing (and perhaps a good set of standard cells you can use for digital implementations with the initial parasitic extraction work done etc). Like any job its a little more standard in practice and bit less focused on the exotic stuff ;)
Most of the coursework here seems to be very similar to what was available over a decade ago at the state university I attended for graduate school (my concentration was semiconductor device theory related). While I think this material is very interesting I don't know that the demand is going to be there for this type of field. Companies like Intel have dedicated smaller departments for process development which do the more academic work (for example the D1X facility).
My experience with fabrication organization is the need is much more process engineer and technician focused rather than semiconductor engineers. The high volume hires are in improving reliability, reducing cost etc. I don't think you really need the EE degree for this, more likely industrial engineering, chemical engineering or statistics.
This said, Purdue has always had a very strong program in the more device oriented semiconductor courses (Until his passing Robert Pierret the fellow who wrote some of the best and most used grad textbooks on devices called it home).
The linked post suggests banning all content on a domain/site after content which does not render in basic html is submitted and continuing until that site appeals the determination. I don't think that would be a good idea as 1) it may hide content which non-HN users produce and would not otherwise know to appeal and 2) penalize broader domains due to bad content produced by say a single user posting to a multiuser site.
I also wonder what would count as not being usable in plain html. Sure there are obvious examples like the article the post links to which display zero content but what about all of the in-between spaces. As an example, what if a site has textual content viewable as plain html but also very informative figures/demonstrations that require javascript to make some of the points in the piece. Would this content be removed if it was partially unviewable and meaningful information is lost?
If folks do want to move forward with some kind of penalization of content perhaps it would be better to agree to vote down this content as a community practice or have a per submitted article flag that either ads a tag of shame [requires JS] to the title or removes only that single article rather than broader domain/site bans that are permanent until appealed.
Maybe it's worth trying to force the change, but if enough people are able to view the content and like it enough to vote it up perhaps we should also just leave it alone and just deal with the consequences of choosing not to run javascript and let everybody just view potentially valuable content that they can see.
There is a service I do like from https://tapiriik.com/ that will sync all your fitness data across a bunch of common fitness apps (it helps when all your friends want to link up for activities but nobody agrees on a single tracking platform). One of the sync options is just to directly download all the raw datafiles to dropbox which is pretty convenient.
If none of those sound good you could roll your own from the source code to tapiriik which is available here: https://github.com/cpfair/tapiriik . It does use some hacks to get around garmin not making all their APIs easy for personal development.
Fun fact, the government opinion for patents for the government and its contractors is also that the federal government cannot be found to infringe on patents either. At most they say they voluntarily choose to provide reasonable compensation. This especially applies if the use of a patent is deemed to be in the interest of national security.
This said, its basically a giant signal mux system run into a main block, you'd be pretty limited on what preselected signals are available at a time. People were also reasonably careful not to give entire busses of signals at once.
Some chip designs make use of purchased IP which is at times VHDL. Heck some unit owners and architects even experimented with HLS (High Level Synthesis) using SystemC for part of the graphics hardware and a few units still have state machines which automatically translate from a DSL or word macros.
I do think both of the trends people are identifying hold true though. US is more verilog than not, Europe I see more VHDL than verilog. US exceptions are typically FPGA developers and defense contractors (but definitely not universally).
In my opinion I find systemVerilog to be much easier to design in with less verbose syntax, better tooling and some nice constructs that make realizing design intent easier. systemVerilog always blows away VHDL in testbench design and general verification environment support. I would never wish designing an elaborate testbench in VHDL on an engineering team. VHDL does have some advantages if you have requirements to do a lot of formal property verification though.