roadbuster

"Processor-in-Memory", is an age-old idea which was even explored in a doctoral thesis from 1998: "Computational RAM: A Memory-SIMD Hybrid"*. At the time, the motivation was, "Between a DRAM chip and a microprocessor mounted on a circuit board, we can only get a few hundred megabytes per second of bandwidth. However, inside the memory chip itself, there's hundreds of gigabytes (terabits) of bandwidth available, so why not move some of the logic there?". And then the author pushed it to the extreme where there was a wide array of 1-bit processors at each column of DRAM. (Note: the reason why true PIM isn't viable is because of the radically different semiconductor process used for DRAM vs. high-speed digital logic, i.e.: your digital logic circuits will perform poorly on a "DRAM process").

The designers of HBM5 had the same observations and thought, "why don't we put a logic chip at the bottom of the stack of HBM DRAM chips and get extremely high memory bandwidth?" But, in looking at this, you'll also quickly realize this is almost exactly what Intel and Micron pitched 15 years ago as Hybrid Memory Cube** (which lost on the market compared to the simpler, less costly, and more flexible alternative, HBM)

* https://www.eecg.toronto.edu/~stumm/Theses/Elliott-PhD98.pdf

** https://en.wikipedia.org/wiki/Hybrid_Memory_Cube

The only way to achieve this is to either put a runtime software check on a variable whenever it's assigned/used, or to literally add hardware support in processors themselves which literally throws an interrupt when a "neverShallBeZero" variable is assigned to zero.

There's no viable way to statically prove at compile-time that these variables will never become zero at runtime, ultimately forcing a system of endless runtime checks (be it software or hardware)... which is why processors already throw exception interrupts when division by zero is attempted.

Indeed, this is a problem for an energetic student who has free access to every tool in the Cadence, Synopsys, and Mentor portfolios: take the GDS-II layout, run it through extraction, generate a netlist, convert to higher-level blocks ("netlist-to-gate recovery"), translate to RTL HDL, then attempt to work out "what it does."

This is just a job posting in disguise for Jane Street: solve the puzzle, get a call from one of their recruiters.

Great project & article. Beyond the use of verilog, I couldn't find a description of the EDA stack. What tooling is used for the physical stages of design: place & route, LVS, DRC, and electrical circuit simulation (SPICE)?

> I don't get how this is unique to GPU clusters

It isn't, and you're right. This is just a long-winded article by someone who thinks they've come across a deep, crucial insight.

I witnessed a bank foreclosure stemming from large, unpaid loans to a lumber mill. The bank absolutely didn't want to take possession of the operation, but had no choice when the founder decided to call it a day.

The bank had no idea what to do with finished lumber sitting in the drying ovens, let alone the entirety of mill infrastructure itself. After struggling to find a buyer, they hired the founder as a consultant to handle liquidation. The same would happen with a repossessed datacentre.

There is no substance. It's navel-gazing dribble.

The "about" section of the website is equally vacuous:

    SmolNero is a philosophical startup rooted
    in first-principles thinking.

    We explore how humans relate to technology—
    how we speak to it, depend on it, thank it,
    and sometimes forget it’s there at all.
    
    We don’t claim expertise. We see ourselves 
    as translators—working at the crossroads of
    emotion and programming, curiosity and care

(The two M-dashes are also suspicious)

If there weren't "clear owners," who was approving code changes for merge?

Every other major arm of Microsoft has been tasked with burdensome controls over tracking any and all production changes to source code, but Github was operating without a useful system and record of ownership for nearly 80% of its repos (11000/14000)?

3000 words which can be distilled down to 10:

"Cream and egg yolk are expensive; industry tightens its belt."

> It really wasn't a bad operating system

It was a wonderful operating system. It provided consumer desktop essentials (Plug & Play, DirectX 7, ACPI power management, Windows Driver Model (WDM), and support for consumer I/O interfaces like USB and Firewire) alongside a modernized UI, all running atop the NT kernel. I was extremely lucky to receive a free copy of Windows 2000 Pro as a student, because I rode that horse for years.

Then Microsoft added a green start button and dark blue backgrounds and packaged Win2k for home users as Windows XP.

Looking at the categories should tell you what happened (lifestyle & fashion, finance, travel, parenting, food & recipes):

They moved to Youtube/Instagram/TikTok for better reach, a larger, total audience, and improved monetization

I think you are taking an excessive interpretation of what was suggested.

Let's level-set on the issue: Of late, GH has suffered a continuous stream of noteworthy outages. It is hypothesized the underlying cause of the instability has been the dramatic rise in submissions from coding agents ("AI"). The open question is how (or whether) GH can get load at a manageable level, with the proposal being, 'don't immediately allocate build/compute resources against any and all submissions.'

I don't see why that is equivalent to rampant disenfranchisement in the open source community. I believe what people have in mind is closer to, "don't immediately trigger an expensive build process as soon as someone submits a pull request."

> would break the entire model

The "model" - GH effectively allowing an overload of their infra - is already broken

> How would a random kid in a 3rd world country ever get noticed enough to enter a trust circle

By submitting a quality change with a clear description, preferably with unit tests? Is that no longer considered an acceptable hurdle?

I think Clearmotion has a very interesting technology and product (ride stabilization), but let's paint a full picture here: the company was founded in 2009, took on $370 million in funding, and only recently landed large contracts (a $1 billion dollar deal in 2023 with Chinese auto manufacturer, Nio).

I'm sure they were in a constant struggle for survival and had to "move fast" to stay afloat, but their technology is more than a decade in the making.

Yes. But, looking at BRCM/AVGO's stock chart, I may have made a mistake.

Yes, that's the issue: the (thick) solid grey "major axis" lines on the background seemed to be a wire.

If I could make a recommendation, get rid of the grid lines entirely and only have 'dots' at regular spacing. Here's what Cadence Virtuoso looks like (the most popular circuit schematic tool for integrated circuit design):

https://www.eecs.umich.edu/courses/eecs311/f09/tutorials/cad...

I worked on deep sub-micron, full custom mixed-signal integrated circuits for more than a decade, and I can't pass the first level.

> Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).

Certainly:

(a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied to the signal input

(b) When the gate (input) is driven high, the nMOS transistor turns "on," connecting the output to the source (which is grounded). This acts as a "pull-down network"

(c) When the gate is driven low, the nMOS turns "off," leaving no connection to the output. This is equivalent to a "high-impedance" / "unconnected" / "Z" output

Fails 1/2 tests

(Edit) - I thought the light grey, thick line on the background grid was a wire from "input" to the transistor's gate. It is not. You need to explicitly add a wire from "input" to gate :\

They certainly have, but the general idea is to first use stealth jets to bomb defensive systems (including radar observability) to conquer the skies, and then you can fly around somewhat freely. While SAM technology has improved, so have America's observability and stealth bombing capabilities. It will be interesting to learn the context and sequence of events which led to an F-15 being shot down by enemy fire.

(In 1991, the United States relied on the F-117 Nighthawk to penetrate Baghdad and launch salvos against radar and SAM sites. Simultaneously, Tomahawk cruise missiles were fired against similar communication and defense sites. In this war with Iran, the F-35 and B-2 have been used for stealth missions).

During the entire gulf war (Iraq, 1990-91), only two F-15s were shot down via surface-to-air engagement. At the time, Baghdad was known to have the highest density of SAM protection out of any city in the world.

An F-15 being shot down in Iran after weeks of strategic bombing of their anti-air defense systems is not a good sign.

> The Claude C Compiler illustrates the other side: it optimizes for

> passing tests, not for correctness. It hard-codes values to satisfy

> the test suite. It will not generalize.

This is one of the pain points I am suffering at work: workers ask coding agents to generate some code, and then to generate test coverage for the code. The LLM happily churns out unit tests which are simply reinforcing the existing behaviour of the code. At no point does anyone stop and ask whether the generated code implements the desired functional behaviour for the system ("business logic").

The icing on the cake is that LLMs are producing so much code that humans are just rubber stamping all of it. Off to merge and build it goes.

I have no constructive recommendations; I feel the industry will keep their foot on the pedal until something catastrophic happens.

> All it really shows is that the “poor” are getting milked for everything they earn and own

How are you concluding that? The only way I can see that could be true is if the bottom 50% has shifted their meagre savings to spending in an effort to stay afloat.

I find this to be dubious because the bottom 50% was never saving much at all in the first place. For context, the median income across planet earth is $850 USD _per year._ There's not a lot of room at the bottom for savings.

> Whenever a new layer of abstraction is added

LLMs aren't a "layer of abstraction."

99% of people writing in assembly don't have to drop down into manual cobbling of machine code. People who write in C rarely drop into assembly. Java developers typically treat the JVM as "the computer." In the OSI network stack, developers writing at level 7 (application layer) almost never drop to level 5 (session layer), and virtually no one even bothers to understand the magic at layers 1 & 2. These all represent successful, effective abstractions for developers.

In contrast, unless you believe 99% of "software development" is about to be replaced with "vibe coding", it's off the mark to describe LLMs as a new layer of abstraction.

> [Synology] comes with dedicated Time Machine support

Your umbrance is with Synology, not Apple.

Apple raised security default configurations in Tahoe. That led to a config breakage with NAS devices which rely on relaxed security configurations.

I agree Apple should publish a technical note / changelog of config changes such as this one, but Apple has never implied to users they'd carry a support burden for any/all third-party hardware vendors. To the contrary, they've notified users that you're meant to consult with your NAS vendor for configuration steps:

> Check the documentation of your NAS device for help setting it up for use with Time Machine

https://support.apple.com/en-us/102423

Acknowledged. Thanks for pointing that out.

It's a hand-waved estimate, but let's recognize that Apple actively plans on killing support for NAS targets for Time Machine:

> Time Machine backup to NAS devices over Apple Filing Protocol (AFP) is not recommended and won't be supported in a future version of macOS.

https://support.apple.com/en-us/102423

> For someone using consumer technology on a consumer laptop

Mounting an SMB share on a Synology NAS to use as a Time Machine backup target is not what most users would consider "consumer technology."

Article title is a bit dramatic. The summary seems to be: for the 5% of users who back-up to a network share (rather than direct-attached storage like a USB hard drive enclosure), Apple's default SMB configs on Tahoe are strict and won't work out of the box with many common NAS solutions.

Apple should document such changes, but, looking at the post title, you'd think they were silently corrupting data during restoration.

> Forget to provide paper in toilets

The world's greatest spy agency at work.

- Power fail-over (battery + generator backup) in every house?

- Could get expensive flying a technician to every household to upgrade hardware in the racks

- Probably don't want everyone at home having physical access to storage devices

- Massive theft risk

- Homeowner's insurance would probably be irked

It has less to do with "oligarchs" and more to do with protectionism over domestic industry: retain jobs in America, preserve worker income taxes revenue, capture taxation of corporate profits, tilt the scales in favour of an American business becoming a global exporter of their products, keep development of high-tech assets under American regulatory control.

This is a well-written, well-researched piece, but some of the narratives are off the mark. For example:

> Phase 1 (Courtship, 2010-2014): TSMC needed Apple for legitimacy

TSMC was already the world's largest pure-play foundry long before Apple walked through the door, controlling more than 50% of market revenue. Although vertically-integrated microprocessor businesses had better-performing processes (Intel, AMD/IBM with PD-SOI), TSMC was head of the pack in the foundry world (competitors: UMC, Chartered, SMIC, etc).

> What if Apple chose Intel in 2014?

How would they have done that? Intel didn't even offer a foundry service at that time, and it would have taken years for Intel to adapt to a foundry model (one which publishes a "process design kit" for use by industry-standard EDA software to design and simulate circuits).