Can you reverse engineer an ASIC? | Hacker News Reader

Can you reverse engineer an ASIC?

blog.janestreet.com

119 pointsbschne87 comments

I reverse engineered the Game Boy from pictures of the die - https://github.com/aappleby/metroboy - so yes, it's totally doable. It is also incredibly tedious and frustrating.

Not sure if that gives me an advantage in this challenge, but I have too many things to do already. :D

Earlier this year I watched a video from a conference where a researcher took a die shot (one of Ken's I think) and then did guided learning by identifying on the image which were the different layers, metals, and layout of the gates on the die. The machine learning algorithm could go off and identify other gates and provide a netlist(?).

I've tried searching REverse, and some of the hacker conferences from January, but haven't found it yet.

and of course I find it...

giulioz: MMO-CHIP: From Microscope to Verilog in an hour[1]

source code is on github[2]

[1] https://www.youtube.com/watch?v=5211iYEqnzo [2] https://github.com/giulioz/mmo-chip

seeing this was done 5yrs ago. Is this easily recreatable by an AI model nowadays? If so, what does it make you feel?

I thought the article was going to be about how people scan chips

Rapid Chip Reverse Engineering Using Laser, Focused ion beams, and Scanning electron microscope https://academic.oup.com/mam/article/30/Supplement_1/ozae044...

FIBs are also used to test modifications before doing a respin. I'm still in awe that matter can be manipulated so precisely

FIB is awesome but there’s nothing easy about it, and the success rates are not super great.

At my uni, 15 years ago, one postdoc reverse engineered NVIDIA chip and wrote more performant compiler. He did that by connecting oscyloscops to all chip's outputs and started with applying random current on inputs. Using ML and his genius he rediscoverd all opcodes including a few hidden ones. Eventually he got hired by some company that was doing a lot of GPU on supercomputers.

You can't do that by applying random inputs to any single-chip GPU - it has far too much state. I can see that perhaps it worked on some of the early multi-chip cards - where one chip was a texture sampler, and so on.

You'll have more luck reverse engineering the software driver first. They're not hidden, you can just open the driver files in Ghidra, the almost-universal tool for open-sourcing proprietary code. Hidden opcodes can be discovered first by just trying all the opcodes you couldn't discover any other way. You only need to go to the physical level if they're really hidden.

To be fair, Ghidra was released in 2019 and in general knowledge was still hard to find even back in 2010 I feel (well, compared to 2026 in the age of AI)

Before that there was, and still is, IDA Pro. Works largely the same but costs a lot, on the order of $1000/seat/year. Useless for hobbyists unless pirated, but reasonable if it's your job. Probably had academic discounts.

Also a few free-but-cut-down versions like 5 (which still recognizes MS-DOS executables). I'm not going to recommend downloading it from any of the locations mentioned here but it's out there: https://reverseengineering.stackexchange.com/questions/19179...

Small pedantic nit: Open-sourcing is not the same as reverse-engineering.

We are taking back control of our computers by force.

There is absolutely no way that happened. 15 years ago, we're talking Fermi class GPUs and chips with hundreds of millions of bits of on-chip state and much more if you include the DRAM.

You can't tease out the right information by applying random inputs. Which input would you even use? The PCIe interface? You'd first "randomly" need to get past its complex training sequences...

Your postdoc probably wrote micro-benchmarks of some sort. That is a common technique.

And you don't use an o-scope in anycase, since you'd need...what...a thousand of them to watch all the signals. You'd use a logic analyzer. I think I read somewhere that those older nvidia chips had something like 2000 BGA balls, and Tektronix does make an LA that can scale to 2000-something channels (TLA7000), for a modest US$500k or so. Then you gotta figure how to mount the thing to attach the probes.

So...agreed...far more likely there was a software solution of some kind if this happened.

You might is they included DFT (design for test, stuff to make sure when you make a chip all of it actually works) - a scan chain thru all the internal flops will provide you with info about the internal flops and how they are connected - reverse engineering this into a model of reality would certainly be extremely hard, but maybe not impossible

While that's theoretically possible, it's even harder than trying to do it over, say, PCIe, because the latter at least still has a higher meaning to it while scan chain FFs are just grouped based on spatial proximity.

And of course that's assuming that a) the JTAG port is accessible on these boards and b) the raw scan chain access before scan chain compression hasn't been fused off or isn't locked behind some authentication protocol.

So, no. That didn't happen either. :-)

“oscyloscops” is a way better spelling I gotta say.

sounds like a mythical creature hahaha

> He did that by connecting oscyloscops to all chip's outputs and started with applying random current on inputs

This is absolutely not how reverse engineering a digital logic ASIC works.

Either the story got embellished through retellings, or this person was a fantasist.

There are people who hack on GPUs but it’s done at the software level.

I did get a kick out of imagining a scene where someone is trying to connect an oscilloscope to a circuit board to reverse engineer the CPU opcodes. That’s like the CSI: Miami version of what this would look like.

Many laymen confuse logic analyzers with oscilloscopes. Don't take it personally - the person you responded to is clearly not a native English speaker.

You absolutely can reverse chips with logic analysis. It is big business in some parts of the world.

with very, very expensive logic analyzers... But yeah, nothing weird here. Plus OP was retelling a story of someone else doing it, while probably not being a specialist in this field. So I wouldn't take the "random inputs" part literally.

> with very, very expensive logic analyzers... But yeah, nothing weird here.

You can’t simply get an expensive logic analyzer and probe PCIe or memory buses at these speeds. There are expensive custom fixtures that need to be made to even begin to be able to probe at these speeds without disturbing the circuit so much that it fails to work. This isn’t like probing the I2C bus on a raspberry pi. It would be like connecting to the pins under the chip. It’s fantasy.

It’s also illogical. If you have a PCIe device, you plug it in to a PCIe host and use the host to interact with it. You don’t start probing pins and trying to apply signals to it.

Your pessimism belies a distinct lack of experience, if not also a dearth of imagination.

Harnesses for such things are not cheap, nor are they something you can just order from Reichelt. But, I assure you, there are reverse engineering labs in the world that can do this. There are technicians who think nothing whatsoever of de-soldering a BGA and using microscopes to rig things up. They do it before lunch, even.

The OP may have some details wrong - they're clearly laymen describing an anecdote - but that doesn't mean for an instance that this "isn't possible".

There is always a higher-speed logic analyzer, capable of operating faster than the consumer device under test. That's how the consumer DUT's get tested at the ATE, in the first place ..

> Your pessimism belies a distinct lack of experience, if not also a dearth of imagination.

You keep missing the point and trying to insult my experience in the process.

We're talking about a university student and CPU opcodes. The whole side story about probing the chip is completely irrelevant. This is a software task.

> But, I assure you, there are reverse engineering labs in the world that can do this.

We're talking about a university student.

> There are technicians who think nothing whatsoever of de-soldering a BGA and using microscopes to rig things up. They do it before lunch, even.

I'm talking about the fixturing required to actually probe those pins. Replacing the BGA is the easy part. You can't probe a large BGA by having a tech remove and replace it. The contrast between you trying to insult my experience while not understanding the task at hand is truly something.

You've chosen a weird hill to die on, given how much you're arguing things that have no relevance to the story.

Maybe your university students aren't as well-funded as my university students, ever thought of that, huh? Maybe your universities are lagging behind the state of the art in the rest of the civilized world. Maybe, you just don't know enough about this subject, actually.

>I'm talking about the fixturing required to actually probe those pins.

This just isn't as impossible as you claim. And, there are plenty of reasons to do it.

Just because you can't imagine it, doesn't mean someone else hasn't already actually done it.

Upvoting this purely because I want to see you two argue more hahahhaha

> You absolutely can reverse chips with logic analysis.

You are not going to reverse engineer a GPU with a logic analyzer and by applying currents to pins.

You could replace oscilloscope with logic analyzer in the comment above and nothing changes. It’s a fantasy story. The GPU I/O is high speed PCIe and memory buses.

If you want to explore the chip you connect it to a PCIe host and use the host. Connecting logic analyzers and applying current to pins does not make sense on any level.

Also, if you think probing high speed signals like PCIe or memory buses with logic analyzers is easy, you’ve probably never tried it. The equipment needed to do that properly is incredibly expensive because even probing those buses slightly incorrectly or with cheap probes will make them fail to work at the speeds they use.

I use this type of equipment every day. I'm aware of the expense - nobody said it was cheap to do this kind of work.

You might be thinking that the hobby-level logic analyzers you're used to, are what folks who are serious about doing this kind of work would be using. Just, no.

>Connecting logic analyzers and applying current to pins does not make sense on any level.

Tell me you've never fuzzed a chip without telling me you never fuzzed a chip.

Nobody said it would be easy or cheap, or that fuzzing is the only way to do it. The OP may not have had all the details correct.

But, you certainly can reverse engineer high-density digital electronics this way.

> You might be thinking that the hobby-level logic analyzers you're used to, are what folks who are serious about doing this kind of work would be using. Just, no.

No I'm not. I'm referring to the logic analyzers and probes, and fixturing that would be necessary to probe something like this.

It's not as simple as saying "wouldn't be cheap". I'm saying it's virtually impossible for a university student to do for fun with the resources available to them.

> Tell me you've never fuzzed a chip without telling me you never fuzzed a chip.

Please don't be snarky. Also please don't take my quotes out of context to try to attack a strawman.

I'm talking about the comment thread we're responding to about someone reverse engineering the opcodes by applying current to the pins.

Nobody is going to be fixturing up an nVidia GPU chip, acquiring enough probes and logic analyzer inputs to measure it, then applying currents to pins, just to reverse engineer the opcodes. You're off trying to argue something else to show off your knowledge on the internet, but you've missed the point of the thread.

If someone wants to reverse engineer a GPU, the first thing you do is plug it into a system and access it through software. Nobody is going to connect logic analyzers to a million pins and re-invent PCIe signaling just because it's technically possible to do.

Your extreme claims that "nobody is going to do that", while I have actually seen people doing exactly that in modern universities and other reverse engineering institutions, just renders your stubborn know-best boring.

Yes, people do this. Yes, it is a lot of tedious work. PCIe signaling is not a panacea - there are reasons to fuzz like this.

I've also seen folks break out a tunneling electron microscope to dig deeper on de-laminated cores.

>I'm saying it's virtually impossible for a university student to do for fun with the resources available to them.

Now who's inventing straw man claims? "For fun"? Yes, for fun. "For profit"? Yes, for profit too. At universities? Yes, at universities.

Just give it up. The world is big.

One other bit in support is that the person you’re replying to read “university student” but OP said “Post-Doc” which I guess technically is a student at a university but a post-doc EE is an exceptionally skilled and specialized role who’s likely been working on that specific problem for 8+ years.

I mean, there are universities with hardware reverse engineering labs in operation since the very, very beginning of hardware.

I’m only persisting with the argument because the myopia is revealing.

Err how would one even connect an oscilloscope to these chips, since there are only a few pins but and is digital information in very high speed?

Thank you for taking your time to squash another potential "urban legend" in the making. We've got enough of them already in tech.

Detailed write-up please, or it didn't happen. At least not as described.

Really simple ICs with a few counters etc in there might be possible to RE this way. Complex ICs with lots of internal state, memory blocks etc like a modern-ish GPU? Not a chance.

Some hybrid approach? Software fiddling with the chip's internals, with say. a big FPGA attached to physically probe outputs? Architecture docs, and maybe some IC die shots at hand? Perhaps (hence my ask for "detailed").

Sounds like requiring the kind of hardware setup that would not be available to uni students.

I've looked at Visual 6502 and it's way beyond me. I've even looked at the scans where it shows how they severed the connection to disable 6502 decimal mode on the NES.

To be fair, the 6502 is very dense, and very hand optimized.

Modern systems tend to use "standard cells" for logic which is a lot more digestible.

The original NMOS 6502 also used a lot of rather weird dynamic logic which can't easily be represented as standard digital logic elements. Some details here:

http://www.aholme.co.uk/6502/Main.htm

Solved it. Took me ~6 human hours, over a total of 24 hours. But it was NOT easy!

I've been making chips for amost 30 years, and I run the https://github.com/smprather/engineering-loadout project, so I had all the tools sitting at my fingertips (KLayout, Surfer, Icarus Verilog, etc).

Pretty same tool used to me.

(A crash course in how chips get made)

That paragraph + illustration is one of the simplest, concise, easy-to-grasp descriptions of IC design process I've come across. Nice!

Now the reverse: what I'd really love is a free (libre) automated toolset to go from IC die shot(s) -> transistors+interconnects -> gate-level schematic (logic gates & flipflops). Person interested in RE a chip's function can take it from there.

To me, the whole "here's a section of the die photo" to "that's an n-bit adder" etc step is like black magic. Not to mention extremely tedious.

Get that to a higher-level view easy, and it would be much more doable to work out function of each element.

Getting a logic-gate-level netlist from a GDS is trivial with industry standard chip design tools. Circuit designers do this every day. The hardest part will be reverse engineering the functionality.

I wish I had more time and I'd throw Calibre at it.

It's even easier in this case because they've included the original verilog source ....

No, that's for the warmup. The real puzzle only has a .gds file available.

Indeed, this is a problem for an energetic student who has free access to every tool in the Cadence, Synopsys, and Mentor portfolios: take the GDS-II layout, run it through extraction, generate a netlist, convert to higher-level blocks ("netlist-to-gate recovery"), translate to RTL HDL, then attempt to work out "what it does."

This is just a job posting in disguise for Jane Street: solve the puzzle, get a call from one of their recruiters.

Nope. I work at Cadence and literally have free access to every one of our tools, but I didn't use a single one of them to solve the puzzle.

The Last Starfighter :).

No need for Calibre. Me + KLayout + Claude had a verilog sim of the example vcd input and gate-level netlist 30 minutes after I cloned the repo.

In a simplified scenario (not too far from this)? Yeah, we've done that in CTFs almost a decade ago.

https://blog.dragonsector.pl/2017/10/?m=1

From where do I know the name Dragon Sector and q3k? You aren't the ones who hacked the train DRM, are you? Or maybe active in the demo scene? Or maybe I'm just confusing you with TRSi?

Maybe. :)

Hasn’t Ken Shirriff been doing this for quite a while? (:->

I'm too busy trying to reverse-engineer the Intel 8087 floating-point chip, although it would be interesting to look at this puzzle chip.

I wrote a guide for newbies to learn

https://siliconzoo.org/tutorial.html

looks like they didn't post any blog post about 2nd NN challenge (https://huggingface.co/spaces/jane-street/droppedaneuralnet)

I was waiting for some writeup about permutation decyphering

Is there something like an Extract-SPICE tool that takes a circuit and gives you back a text rendering of it ?

Practically No, the stack-up of metal layers often hides the gate structures underneath, and the billions of process cells may not all be the same.

Theoretically Yes, as an ion-beam-mill and electron-microscope combination machine can slice up semiconductors layer-by-layer. Given these machines can often also give precise x-ray analysis material data, the exact makeup of the chip can be extracted by competitors given enough time. =3

Now you're making me imagine some kind of 3D-scanning, confocal x-ray fluorescent spectroscope.

Or maybe some kind of hybrid of x-ray microtomography and spectroscopic analysis all in one.

But, maybe the energies involved would be about the same destructive power as some microtome slicing technique...

We already know that X-rays don't destroy chips.

I was thinking of the kind of high-energy photon sources that sprawl across a large laboratory campus behind rings of security fences.

These things can definitely erode the targets. Tomography experiments have to think carefully to optimize the set exposure angles used during a session, because the target degrades more with each shot.

> Theoretically Yes, as an ion-beam-mill and electron-microscope combination machine can slice up semiconductors layer-by-layer.

You may not even need anything as fancy as that - many microchips can be delayered by a skilled operator using mechanical polishing processes.

Yes. There is exactly that, and we call it an "extraction" tool. It takes a GDS (text representation of shapes in the physical layout), and gives you back a "netlist" (text representation of components and connections in a circuit schematic).

Circuit designers use these tools basically daily for two reasons - the first is Layout Versus Schematic. We want to make sure that the physical layout matches the schematic, so the tool turns the layout GDS into a netlist and compares that to the netlist created from the schematic (basically a diff, but more complicated). The second is so we can run simulations that take into account the "parasitic" resistances and capacitances of the wires and metal shapes in the physical layout. It's basically the same procedure as LVS with an extra step that analyzes the metal shapes to determine said R's and C's.

yes, but at the transistor level .... it has no idea at that level how those transistors are arranged into gates directly

I take it back, it's a sky130 .gds the gates are explicitly in there

In fact if you have the sky130 libraries installed (it's where I'm working) you can get a spice netlist out of it in about 10 seconds - really they should have flattened it

That would have added a definite layer of complexity, but really just a token/cpu drain on the puzzle solver. Had they done that, I would have had Claude write a "gds matcher" that took the gds files of the sky std-cell lib, and located matches in the full gds, and produced a hierarchical def. It would have taken me 5 minutes to describe it to Claude/GPT (which they ok'd for "tool creation"). So it adds a lot of cost to solve the puzzle, but no real complexity. I'm glad they didn't flatten it.

The tools can definitely recognize static logic gates purely from the topology (nothing special in the GDS needed). I don't know that I've tested it for anything more complicated, but as you've pointed out, if the hierarchy is in the GDS it's trivial to recover

What prerequisites I need to solve this puzzle? I don't have much knowledge in electrical engineering.

It’s hard without some basic knowledge maybe this can help https://siliconzoo.org/tutorial.html

I encourage you to try, but honestly, with almore 30 years experience making chips, I would still classify this puzzle as "pretty damn hard".

That sounds like a fun challenge. Feels a lot more tractable than the neural net one.

30 minutes with /goal for the solution from Sol w/ high.

Man, these guys always have insane puzzles. What the heck.

people who can do this stuff are super-smartypants

but reminds me how we're going to find out on an industrial level when the Saudis give China some nvidia chips they were grifted

they've cloned lots of chips before but nothing that advanced

China has no shortage of Nvidia chips. It costs nothing (relatively) for someone to just buy a 5090 off the shelf and send it there.

You can do this. If you commit the whole next month to it you'll make quite some progress. But you won't.

I'm a chip designer, back in the early 90s I visited a small silicon house who were doing some work for us, their boardroom table had been taken over by a giant sized photomicrograph of IBM's VGA chip and they had a bunch of summer hire grad students tracing wiring and matching standard cells (easier back then because we only worked in 2 layers of metal).

They weren't trying to steal IBM's design, they already had one of their own, what they wanted to know was "is there any as yet unannounced functionality in the IBM VGA chip?" they didn't want to be caught out when some unknown registers popped up. Of course it turned out there was as yet unannounced functionality - but not by IBM's design, more because of the orthogonality of the design - MODE-X was discovered and became the basis for DOOM's speed, anyone who didn't support it lost out

MODE-X launched 1,000 ships too with the demoscene.

They did give the chips to China, but they didn’t work. Turns out they’d first taken them to the basement where someone cut them into pieces before sending them to China.

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