metaphor

A bit tangential, but can anyone in the know of UPS inner workings explain why the applicable tracking number[1] would reflect a "Shipped" status 3 minutes before "Label Created"?

https://www.ups.com/track?loc=en_US&tracknum=1Z9X26374278728...

At 1:42 mark of the news broadcast[1], a snapshot of order details shows Sold by: Amazon.com Services LLC for both a $398 memory card and $6,498 camera.

[1] https://youtu.be/N-boHgrQ6QQ?t=102

You're probing for an easy answer because you think one exists that'll be as easy as handling the commodity 100mil interconnect you've been playing with. But the fact is a minimal satisfactory answer resides in the 2nd level of nature's bowels where the simple conservative models of Ohm's law and the laws of Kirchhoff that you were taught in basic physics start to break down as a useful standalone tool and must be supplemented with more complex models to remain consistent with real world observations. I'm not even talking about Maxwell's equations in the raw either...we're still several orders removed, sandwiched in a domain where lossless transmission line theory and lumped-element modeling still hold. Still not ringing any bells? No worries...most practicing EEs are quite deaf to them after college as well.

If you insist on settling on an answer constrained to classical 1st-order models, then you're in for a treat: everything should just work! The guzzintos perfectly match the guzzoutas, first law of thermodynamics is demonstrably preserved, motherhood and apple pie, happy endings.

Except that's not how the real world works...and it almost certainly won't meet any pragmatic definition of commercially reliable at the limits you're wanting to probe at. But why trust what I have to say? You have an entirely capable Artix-7 dev board at your beck and call. And you have an oscope that'll generate eye diagrams all day to your heart's content. And the Pmod interconnect is so trivial that you could even hack together a throwaway DUT load...or why bother with that when you could use one of your existing Pmods as a real world DUT to characterize?

I thought I left enough breadcrumbs for the incidental reader to self-service on how deep down this infinite rabbit hole will be sufficient to grasp the magnitude of the questions being asked, and I thought my language was appropriately tailored. Maybe not. Here's a few more courtesy hints:

1. The first remark was to steer towards qualitatively thinking about the role of parasitic inductance and how this parameter will dominate the interconnect at higher frequencies as skin effect kicks on. It's worth noting that you'll be quickly sucking hind tit attempting to control impedance through a board-to-board interconnect of this design, which immediately kills reasonable prospects for a huge chunk of the application space that FPGAs are chosen as a viable host for right out of the gate!

2. The second remark was to kindly say that EEs who care about SI couldn't care less about the fundamental frequency of your digital signal when what matters in practice are the significant harmonics that said signal's edges are comprised of. The term significant here is roughly defined as at least 10%ish of the fundamental's magnitude. To get a feel for the landscape, derive the Fourier series expansion of (keeping things simple) an ideal square wave and interpretation of the rest should naturally follow.

3. The third remark was to establish a ballpark basis for independently sizing up when the convenience of simple 1st-order models start to break down and it becomes necessary as a matter of due diligence to kick it up a notch. Determine the permissible distance your signal needs to travel. Determine the wavelength of the highest significant harmonic of the signal to account for (assume in a vacuum to keep it simple, completely ignoring substrate permittivity). If the ratio of distance to wavelength exceeds 1%, consult with a competent electronics engineer if you objectively care about quality.

That's about the best approximate free answer this engineer is willing to extend. Need better precision? I'd recommend deferring to a billable scientist.

(P.S. only about as fun as trying to explain the merits of idempotency to my wife /s)

Not trying to be unhelpful, but if the assertion was not immediately evident, then you're missing a huge chunk of basic undergrad EE theory that cannot be dismissed as merely academic. I'd recommend reading the spec (it's only 10 pages) and coming to your own conclusions.

To your shift register question---which is the only one with enough detail to afford a quick answer---referencing JEDEC JESD8C.01 § 2.3 Table 2 as basis of comparison: yes wrt VILmax, and no wrt VIHmin...at face value, it doesn't comply with industry standard, but is nevertheless permissible by Pmod spec because, well, it's a shit spec by a sample size of 1 engineer's measure.

To your TinyFPGA question, I don't care to ponder the design considerations (or lack thereof) of arbitrary hobbyist dev boards in the wild. In the nicest way possible, it's a complete waste of my time, sorry.

Suffice it to say the spec's interconnect choice is the primary limiter, compounded by permissiveness in some aspects, poor specificity in others, and the general ease of abusing objective interoperability while still complying with normative language.

I leave it to the passerby as an exercise to consider the implications of the following notions in this context:

1. All real conductors exhibit certain parasitic properties which deviate from an ideal model; whose characteristics are largely a function of physical geometries, relevant material properties, and the signals that flow in/around them; and whose significance is almost entirely dependent on the application under consideration.

2. An arbitrary signal that satisfies the 3 Dirichlet conditions can be summarily expressed as the linear sum of its fundamental and harmonic sinusoidal components.

3. As a back-of-the-envelope measure, transmission line effects cannot be so easily neglected when, in a point-to-point system, the ratio of the distance that a signal must traverse to the wavelength of the propagating signal itself exceeds roughly 1%.

I offer 3 different reasons why FPGAs might make sense to consider:

1. (general) application reconfigurability where the benefits of SRAM performance, integrated hard IP, fabric real estate, and/or cycle-accurate RTL control cannot be easily replaced by other roughly asymptotic solutions;

2. (general) offloading massively/embarassingly parallel compute architectures where commodity GPGPUs are either physically incompatible and/or power-wise too inefficient;

3. (enterprise) overall volume/performance/budget/schedule objectives fall short of the sort needed to justify pushing a bespoke ASIC design through process pipeline.

Relatively speaking, "blazing fast implementations of algorithms" is possible iff the compute bottleneck can be effectively parallelized; I'm not certain what was meant by "hard to run otherwise".

To put this into perspective, reliably clocking a non-trivial FPGA application at 200 MHz is objectively hard in a way that hobbyist types outside of the professional domain can't seem to understand (or arrogantly dismiss). And yet for the right class of problems, such an application may have the potential to put a GPGPU clocked in the GHz to shame on both compute throughput and power consumption fronts.

This talk struck me as conflicting in a sort of have-your-cake-and-eat-it-too kind of way. The wrinkles part[1] summarizes a lot of what this individual is advocating. Paraphrasing (with equivalent liberal handwaving of details as the talk does):

I want to write FPGA code like any other high-level programming language (but quickly dismiss that the hard part of developing native HDL is in fact that it's fundamentally a lot more akin to architecting physical hardware).

I want to use FPGAs because they're powerful (but only when a conceptual design aligns with a traditional microcontroller architecture).

I want to use FPGAs because they're flexible (but I need to nerf proprietary building blocks that endow specific devices with competitive edge, or trade significant performance in other ways to do so).

I want to commodify the development peripheral market (but only if they conform to a certain commercially trademarked and weakly defined spec[2] inherently constrained to low-frequency applications where sloppy SI is presumed to be inconsequential).

I want to standardize high-performance interfaces (so arbitrarily "abandon standards you don't like" and simply write your own, but only if they're not "annoying"...and look like a custom FIFO with specific signal labels).

I'm sure this will be an unpopular opinion, but the positive feedback loop generated around this topic needs a stability check.

[1] https://youtu.be/ME_e06ApxJA?t=2080

[2] https://digilentinc.com/Pmods/Digilent-Pmod_%20Interface_Spe...

I admittedly fail to see how that Twitter remark survives a naive sanity check[1]. What am I missing here?

[1] https://github.com/hzoo

It's difficult to imagine how the underlying fault here is anything other than a latch-up[1] event, likely manifesting on a upstream controller/supervisory chip in the power distribution chain.

The description of this "flea power" reads like some cargo cult narrative that summarily conflates a handful of disjoint electrical characteristics/phenomena. It's like the modus operandi of interwebs consumerism.

[1] https://en.wikipedia.org/wiki/Latch-up

> Just because E.E. or C.E. degree courses mention a topic, doesn't mean that topic all of a sudden becomes exclusive to them.

What country did/do you study in?

In the US, a research university intro course offering that's asymptotic to this book will almost certainly be promulgated by the EE side of the house for reasons like satisfying ABET accreditation requirements or EE programs generally being better postured to support lecture/recitation supplemented by a significant hardware lab component. At Stanford, see EE 108; CMU, 18-240; UF, EEL 3701; and so on.

At my undergrad alma mater, it was the only upper division EE course that didn't have a prerequisite. The senior lecturers who alternately steered the course were notorious for baiting would-be freshmen into taking it early as an effective means to cull the herd. What's funny is CS undergrad advisors publish a suggested sequence with a footnote calling this major course out by name with an explicit recommendation that it "be taken either by itself during the summer or with no more than 13 hours/credits during a Fall/Spring semester."

National labs are indeed above the DoD average, but NAWCAD isn't a state-run university either.

High probability this clown was compensated in a pay band[1] that spans the equivalent of GS-12/13 for the locality[2].

[1] https://www.federalregister.gov/d/2010-22172/p-169

[2] https://www.opm.gov/policy-data-oversight/pay-leave/salaries...

> It calls them "alimentary paste."

Citation?

The article doesn't mention "alimentary paste" anywhere, so your remark comes off as assertive, yet I couldn't find traceability to this term in what I believe to be the applicable federal statute[1].

[1] https://www.ecfr.gov/cgi-bin/text-idx?node=pt21.2.139&rgn=di...

> Now the question: how often do these increase?

With respect to .io renewal on Gandi.net based on personal records:

  US$35.00/yr through 2018
  US$38.00/yr (+8.6%) into 2019
  US$42.18/yr (+11%) into 2021

If I recall correctly, .io renewal was limited to something like 1- or 2-year intervals not too long ago; this appears to have changed, but I'm unsure when that happened.

I apparently didn't catch the part of your previous remark where you alluded to the value of your car, but to be fair, the car insurance industry isn't both heavily regulated and immensely profitable because most people truly understand what they're buying, as a mandatory legal requirement more often than not.

I'm not familiar with how EU/UK differentiates "personal liability" from "3rd party liability" and what all that entails. The parent said:

> $50 a month for liability

...so I presumed a resident of the US.

US car insurance policies vary from state to state, so I'll just say how I understand it in layman IANAL terms.

In my state, personal injury protection (PIP) and property damage liability (PDL or commonly just "liability") coverage are the minimum requirements to legally drive a vehicle. There's also bodily injury liability (BIL), but since my state is what's called a "no-fault state", it's not a hard requirement unless you're a taxi (although my coverage bakes it in; I understand this to be applicable towards passengers).

The parent also said:

> Pleasantly tolerable fee for a day where my car hits black ice and physics takes the wheel

In this case, liability coverage as I understand it won't cover damage to the insured's vehicle while driving, which falls under "collision" and is entirely optional for a vehicle that is outright owned (i.e. no lien on the title) in any US state, as far as I'm aware.

So PIP would cover your injuries, PDL would cover damages to the property of others, "collision" covers your property while driving, and this other thing called "comprehensive" covers your property when not driving...and if that doesn't cover all the medical/property bills, then involved parties are free to sue each other.

> Pleasantly tolerable fee for a day where my car hits black ice and physics takes the wheel

Hope that day doesn't come because, ironically, liability won't cover your losses. It may, in full or part, cover the incidental loss of others impacted, but not your own.

The parent assumes that word wrap, a feature we take for granted today, is even a thing in the editors/terminals of legacy systems that this 80-character rule likely targets.

You've summarily conflated a signal's fundamental frequency with the significant harmonic contributions of its edges.

Take a moment to review ISA v2.01 spec[1] § 10.4:

> To minimize crosstalk between signals and bus reflections, the driver rise/fall rates must be greater than 3ns; only LS or ALS devices are allowed. Faster parts such as F and AS cannot be used to drive the bus.

If you thought it odd that normative language like this explicitly calls out tech by name, then you might have some sense of just how concerned Intel was about interoperability at the time...no thanks to wire coat hanger designers.

Also consider the language of PC/104 v2.6 spec[2] § 4.7, which is probably one of the last remaining modern platforms with native ISA bus integration:

> Whether [ac] termination is needed and where it should be located, is dependent on the specific system configuration and must be determined by the system designer.

Now consider for a moment why this language and the paragraphs that precede it exist in this independent standard. This design is a commidity peripheral that will be integrated into arbitrary systems.

Length matching literally costs nothing...but even this is apparently a "stretch goal" given the obvious fact that this design completely dismissed the normative max 2.5" stub length requirement.

So no, I disagree. For the sake of sensible SI that's too often conveniently dismissed by hobbyists, keep your wire coat hangers in the closet.

[1] https://archive.org/details/bitsavers_intelbusSpep89_3342148...

[2] https://resources.winsystems.com/specs/PC104Spec.pdf

Err...the only thing "modern" about this is you can purchase/fabricate one using new material and components in active production. If a modern cell phone integrated those SMT packages, it'd be the size of a brick, and the PCB itself is vanilla 2-layer Tg130 FR4...couldn't even be bothered with a controlled impedance layout, let alone length-match bus traces. Recently, bunnie talked about one "relatively modern" PCB design element---microvias---and explains why you just don't see them much in OSHW designs[1]...an excellent read if you get the chance. JLC is a well known PCB fab house because their low-volume prices are dirt cheap, not because their process is modern.

[1] https://www.bunniestudios.com/blog/?p=6011

Video of the talk: https://www.youtube.com/watch?v=KClAPipnKqw

Why was this marked dupe? It's a lot more interesting and informative than the OG announcement.

Throwing KVM switching and spreadsheet review into the bag of real world considerations.

> Not really that important. +/-50% is no big deal.

By your anecdotal judgement, sure. But for the rest of industry proper that actually cares about quantitative objectivity, there's ASTA Method 21.3 which supplants "trained tasting experts" for HPLC.

If you don't already have the sort of corporate hookup that the author has (R&S test gear on an ESD mat smells pretty telltale), then plan on throwing down at least another US$3K for a Quartus Prime Standard[1][2] license to PNR this target for shits and grins.

[1] https://www.intel.com/content/dam/www/programmable/us/en/pdf...

[2] https://www.intel.com/content/www/us/en/programmable/buy/des...

Agreed, and brings back fond memories. Elephant Butte and Ruidoso were some of my most memorable camping trips as a young adult. The first time I drove solo for more than an hour was out of Alamogordo to visit a friend in Albuquerque; I never did forget how dramatic the scene transitioned entering the Valley of Fires close to sunset. A few years ago while accompanying my kid sibling to Palo Alto for freshman preview, we detour road tripped into Carlsbad to hike the caverns. The experience flying into SFO a few days later still serves as a reminder of how much I dislike city life.

Worth noting that processed meat here[1]:

> ...refers to meat that has been transformed through salting, curing, fermentation, smoking, or other processes to enhance flavour or improve preservation.

So this isn't just hot dogs, Spam and the like being targeted. Makes me wonder what cancer rates looked like in times long before refrigeration was commoditized.

TBH, Prop 65 in practice confuses me. For example, I have a jar of pickled red ginger in the fridge that I use for kimbap and such with a Prop 65 warning. Listed ingredients are (in order):

  GINGER
  WATER
  SALT
  ACETIC ACID
  CITRIC ACID
  POTASSIUM SORBATE (PRESERVATIVE)
  FD&C RED NO. 40

When searching the database[2], nothing returns for anything on this disclosed list. I'm clearly missing something here.

[1] https://www.iarc.fr/wp-content/uploads/2018/07/pr240_E.pdf

[2] https://oehha.ca.gov/proposition-65/proposition-65-list

Voltaire's perspective[1] struck me as more compelling:

> To-day people complain of a surfeit: but it is not for readers to complain; the remedy is easy; nothing forces them to read. It is not any the more for authors to complain. Those who make the crowd must not cry that they are being crushed. Despite the enormous quantity of books, how few people read! and if one read profitably, one would see the deplorable follies to which the common people offer themselves as prey every day.

[1] https://history.hanover.edu/texts/voltaire/volbooks.html

DARPA Spectrum Collaboration Challenge[1] spent 3 years exploring this space with SDR + AI in a gamified way[2] and announced its winner last year[3].

[1] https://www.darpa.mil/program/spectrum-collaboration-challen...

[2] https://www.youtube.com/watch?v=-a-N8MiMqz0

[3] https://www.darpa.mil/news-events/2019-10-24

I personally don't even like Amazon and have almost completely severed personal market ties to them, but GTFO with "investing right back".

How's that $200MM O365 performing for your enterprise, Navy? Oh, you mean you can't even reliably access email and just about everything broke post-deployment? No worries, just launch in Internet Explorer and it's sure to mostly work!

And how's that polished Teams collaboration suite treating you? A cut above with steamlined mission critical video chat that Skype hooked us up with, yeah? Oh, integrated wiki v0.1 release you say? Too bad, but thanks for the enterprise-scale beta testing, we'll be "investing right back" by providing you with an improved v1.0 release as your acquisition program office approaches a decision to exercise contract options several years from now.

And we're so sorry there's no transportability between this "Teams" and the other "Teams" deployed a few months ago...for everyone outside of your org, it's a transparent technical detail, but since these enterprise solutions are specifically tailored to your needs, just think of this roadbump as a feature!

You mean to say you needed modern source control and continuous integration capability? We're sorry, GitHub wasn't part of the contract. But hey, we know a bunch of your teams are trapped, err, voluntarily embrace our value TFS offering to process the boundless acronym soup of arbitrary work items which replaced equally arbitrary paper forms, and we know you love churning in the latest deprecated release of tfvc because git and all this command line stuff is just so inefficient. We definitely do appreciate the nice collateral revenue that all the superfluous Visual Studio licenses you've purchased through an exclusive BPA for all the managers that don't code but want to feel like they can be on point with their reports, we completely understand what it means to slowly become irrelevant. At Amazon, it's always Day 1, but at Microsoft, we understand progress and know how to get your enterprise to Day 2 and beyond!

And hey, you've got that bleeding edge SharePoint as an alternative "configuration management" tool for all your Word docs and Excel spreadsheets and PowerPoint presentations (we know you really love those) and Project files and Visio diagrams, so no real barriers there, we're here for you!

Oh, and that lean af grassroots devops team that decided it was tired of our subversive lobbying influence by making a suite of modern tools readily accessible and enable a real opportunity to flow comparable to modern agile teams, which was adopted like wildfire amongst the Pareto 20% of your engineering workforce? No worries. It's really not such a big deal that hosting on absurdly crippled AWS GovCloud puts Azure SLA in practice to shame, and it's no biggy that they were the lone entity to embrace a release of GitLab that no longer supports Internet Explorer for the sake of actual sanity and modernity. By the time your competent IT staff pushes our progressive Win10 1909 release into the wild and fixes all the network printers we recently broke, we'll have a plan in place to justify expending 9 digits of taxpayer dollars for capability that's either deficient, broken, or doesn't exist, and we'll be "investing right back" with suggestions of a new requirement that's so entrenched in our proprietary legacy baggage that no one other than us can fulfill it. Those undercompensated government engineers sacrificing career opportunities in a private industry that compensates at least 3x more for equivalent talent are just a number. We, Microsoft, are here to handle all our technical debt just for you!

I swear you can't make this stuff up.

With respect to HPD, one contributing factor per DP 1.1a § 5.1.4:

> There is no mandatory time constraint on the Source Device’s response to a plug / re-plug event, but a Source Device vendor may want to impose a voluntary constraint similar to that for HPD IRQ events (for example, 100 ms) to ensure a good user experience via prompt discovery and configuration of newly attached devices.

There's a lot more going on behind the scenes than mere "scanning for a valid data frame and flinging bits onto the glass", and much of it has nothing to do with approaching technical limits, e.g. the dynamic of multiple product vendors finding incentive to reach consensus in standards development despite naturally seeking to cut each other's throats in the open market.

> Where is "trickle power" supposed to come from? DisplayPort also mandates that DP_PWR not be connected by cables (only intended for adapters / dongles, see § 4.2.1.1 and Figure 4-23).

The answer seems to me unambiguous when considering the normative language in § 4.2.1.1:

> The standard external cable connector assembly must not have a wire on pin 20, DP_PWR.

...in conjunction with the normative definition of trickle power per § 1.4 (my emphasis):

> Power for Sink Device that is sufficient to let the Source Device read EDID via the AUX CH, but insufficient to enable Main Link and other sink functions. For sink to drive the HPD signal high, at least the trickle power must be present. The amount of power needed for the trickle power is sink implementation specific.

(To be sure, Figure 4-23 per DP v1.1a is single-slot PCI "Panel Cut Out Reference Dimensions", so unsure what was meant to be conveyed there).

> Note that EC demands that electronics put in stand-by / "off-mode" may not consume more than 0.5 W of wall power.

...which is ~150 mA at 3.3 V nominal. Even generously derating 30% to account for ballpark efficiency losses, we're still talking > 100 mA budget to support an explicitly constrained requirement. I mean asserting HPD in the worst case is apparently a 36 uA affair.

Anecdotally, I haven't encountered the issue despite a bias towards DP (on advise from a friend in compliance test over a random beer discussion on radiated emissions performance); all my setups discriminate to either dual U2415 or dual U2412M as a matter of personal preference.

Just thought I'd remark in passing because VESA specs never really struck me as being technically egregious in its ambiguity.