A team of senior elite chip designers builds something they already know how to build and everyone goes "wow AI be so powerful".
196 karma · joined March 23, 2026
A team of senior elite chip designers builds something they already know how to build and everyone goes "wow AI be so powerful".
What a lovely euphemism.
Signed: someone slightly crazy.
I detailed the roadmap for custom ASIC design a bit here: https://talesonthewire.com/projects/two_weeks_until_tapeout/... and joining the Tiny Tapeout discord community is a great place to reach out for help.
This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout. :)
Also how much you can fit really depends on the node the shuttle is targeting. So I was in luck that this was on Global Foundries 180nm as you can cram in a lot for flip-flops onto a single tile compared with Skywater 130nm. On the other hand the gates are much slower than on Skywater 130nm.
Hopefully both programs will be around for a while, so if you are still interested when you have more time you can join the shuttle then.