mng2

It should be mentioned that the '100T device pictured actually requires the full paid version of ISE. The free-as-in-beer ISE Webpack only supports up to the '75T. Thankfully Xilinx implemented compatible packages through the device family, so lower devices are a drop-in replacement (mostly).

Maybe one day we'll have a Free toolchain, but FPGA tools are much closer to chip design tools than to compilers, and the space is fraught with patent concerns. However I did read on Deep Chip that some fundamental synthesis patents have been invalidated, which might open up some breathing room.

The hardware sounds dead simple, not to mention cheap. The service is the actual product here.

When I talked to somebody at Blue Waters (petascale supercomputer at UIUC), she told me that they had uncorrectable errors once or twice per day, even with ECC. Blue Waters has 22640 compute nodes that contain 16 cores each (we'll ignore the GPU nodes). So even if your typical home computer had 16 cores, you would expect 12 hours * 22640 = 31 years between uncorrectable errors.

Caveats: most computers don't have ECC, and I don't remember if Blue Waters was completely installed when I visited.

Your comment dredged up old memories about this flight sim pod place. My friend (well, his dad) took us there a few times for his birthday. It amounted to ten minutes or less inside the pod, with primitive graphics and kind of twitchy controls, but it was pretty cool as a kid. Looking back, it's probably the kind of activity you'd book for a teambuilding exercise; it likely cost big bucks.

This would've been mid to late 90s, somewhere in the Bay Area. I did a cursory google but didn't come up with anything.

The comments on this EETimes article[0] are snarky but the criticisms sound cogent to me.

0: http://www.eetimes.com/document.asp?doc_id=1325499

COD is intended for undergrad courses, CA is more graduate level.

I like VHDL, but SystemVerilog does have some very nice features.

Back maybe ten years ago, I was on an AT&T family plan, and the bill had every single text printed out on it. But texts were 10 cents apiece so I didn't really use them.

Yeah, enthusiasts were A/Bing MP3s a decade ago. There are new frontiers now.

Companies like Micron are looking to reduce their exposure to the commodity hardware business by getting more into services. This platform still looks pretty complicated to use, but Micron/Convey would probably be happy to take care of that -- and that's probably where most of the profit is.

I looked at Bowler's thesis. The DAC chips set the performance, the FPGA is just a natural way of interfacing to them.

http://www.nist.gov/pml/div688/grp10/upload/Bowler15_thesis-...

Well, Reagan did tell them to "throw deep".

It made no difference for me. Try it yourself with a control.

The "freeze a big block and cut off the ugly part" definitely works though.

I'm not familiar with the nitty-gritty of the LHC experiments, but in general the various detector subsystems have different response times and rate capabilities. There are certain types of detectors with explicit time granularity (e.g. time of flight) but for most detectors there would be no time structure within a single collision record ("event").

But you could work backwards to make an animation for each event. From a scientific perspective it's not that interesting though.

The trumpet can be played one-handed, actually. Gets a little heavy after a while, but you can rest the bell on the dashboard. Also you won't be able to use the first and third valve slides to correct the lower notes, but who's listening?

Yeah, my hard copy is probably going to show up Wednesday or Thursday. Sometimes I wish the discussion on New Yorker articles would get delayed a week.

A fusion/fission rocket engine using a pinch seems pretty blue-sky at this point, to be honest. Their paper[0] only briefly mentions the main problem with cylindrical geometries: "With a successful Phase II award the team will test at these varying power levels z-pinch processes to drive out the progression of plasma instabilities in a z-pinch process." Pinches are not very good at being stable, and they are what people tried before going to toroidal geometry (tokamaks et al). Of course, for pulsed power you don't need your pinch to be stable for very long, but at our current state of the art it's breathtakingly inefficient.

Fusion/fission hybrids have been mooted for power production, but there are several issues. First, why make your neutrons via fusion when that's essentially the most difficult way to do it? Second, once you put uranium into your reactor, you've got the same nuclear waste problem that you've got with fission, mucking up your arguably-much-cleaner fusion process. So there are significant downsides to a hybrid system.

0: http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/2014001...

The JEDEC SmartBrief is a really great overview of what's going on in the chip industry.

I also like getting Crowd Supply news every so often so I can see what's going on in the hobbyist space.

One of my profs told the class (NucE) that after the cold fusion announcement, people would come around the department to furtively ask for heavy water and such. So you can bet that smart people aren't going to pass up the opportunity to confirm what would be a major scientific discovery.

No, the X200s only came with TN screens. I actually swapped my 1400x900 TN screen for a 1280x800 AFFS. (In order to do this, you have to swap the entire screen assembly for a X200 one, _then_ swap out the standard panel for a HV121WX4-120. You have to do this because the 1400x screen uses an LED backlight.)

That particular screen has horrible viewing angles though, move your head a little bit and the colors shift.

Vivado is good and bad. Vivado's schematic and device views are much better than the earlier FPGA Editor et al. The interface for adding Chipscope debug signals is quite nice.

However there are lingering bugs. The hardware manager crashes a lot if you don't handle your debug nets carefully. My colleague had an issue with constraint priority. I _think_ I've encountered an issue with VHDL synthesis being incorrectly cap-sensitive, but I never bothered to make certain.

Overall it's getting there. The Zynq stuff is neat (once you understand what's going on) but I have some misgivings about the push toward IP cores.

Is Sonic fiber still limited to that stretch of Florence Ave? Wish they'd bring it to more residential areas (I'm in Santa Rosa), but I guess they're focusing on business customers.

You'll need to change the RAM primitive to the Altera equivalent, but it should fit just fine. Then you have to figure out how you're going to interface to it.

The problem is that what we send down cables aren't nice sharp square-edged waveforms. If you decompose a square-edge digital waveform into its Fourier series, you'll find that it takes roughly 10x the fundamental frequency of the digital rate to decently represent the signal -- so a 1 Gbit/s digital signal would take 10 GHz of analog bandwidth. Naturally this is a big waste from a Shannon-Nyquist perspective, so in practice what gets sent aren't nice sharp transitions, but rather curvy ones without so much high-frequency content.

It's still true that there are voltage thresholds at the receiver, but for high-speed digital comms there are now _time_ thresholds. In a transmission line, discontinuities cause partial signal reflections that can show up at the receiver to mess up your day. A more intuitive way to show cable quality is the eye diagram, which tells you if the threshold and timing requirements are being violated.

http://en.wikipedia.org/wiki/Eye_pattern

Edit: But this is getting away from the point of the article, which is that bad terminations cause crosstalk. There's nothing mystical about cables failing ISO specs for crosstalk. I agree with you though that some before/after packet loss numbers would've strengthened their case.

>You can't get the nuanced expressiveness in a crystal lattice that you can in the free space of a vacuum.

Cute, but at the end of the day it's just different nonlinearities in the transfer function. If you like how ancient technology sounds, that's fine, no need to ascribe mystical properties to it.

I've been buying my glasses from Zenni for a couple years now. I'm rather nearsighted (-7), with astigmatism, so I was pleasantly surprised that the optical quality is pretty good. The frames are somewhat less consistent though, I imagine they have multiple suppliers.

The part I like best about Zenni is the oleophobic hard AR coating option. It doesn't cost an arm and a leg, and actually lasts a fairly long time without scratching. (If you wear glasses you know that no matter how carefully you clean your glasses, they scratch. And the expensive coatings flake off.) Now I clean my glasses with soap and warm water in the morning, and the water just shakes off at the end. The anti-reflective aspect is somewhat lacking, but the ease of cleaning is what makes it for me.

I'm not sure what you mean by 'physically reroute traces'. If you mean, physically move a metal trace across the chip, that's not really possible at this point.

One-time programmable devices (GAL and PAL devices that are essentially obsolete, most FPGAs are SRAM based these days) require physical fuses to be blown in order to program functionality. I suppose that's a physical change, but one that's irreversible.

Re (3), FPGA Partial Reconfiguration has been a standard feature on high-end parts for a long time. However I've heard (never used it myself) that the present implementations are of limited utility. Most applications that can afford a high-end FPGA can afford an auxiliary processor for management duties, so self-reconfiguration remains something of a curiosity.

The theoreticians usually figure out what exactly to look at. The experimentalists figure out how to do it, and then carry it out.

A common joke is that you don't let the theorists anywhere near the apparatus, because they'll break things.