Vivado is good and bad. Vivado's schematic and device views are much better than the earlier FPGA Editor et al. The interface for adding Chipscope debug signals is quite nice.

However there are lingering bugs. The hardware manager crashes a lot if you don't handle your debug nets carefully. My colleague had an issue with constraint priority. I _think_ I've encountered an issue with VHDL synthesis being incorrectly cap-sensitive, but I never bothered to make certain.

Overall it's getting there. The Zynq stuff is neat (once you understand what's going on) but I have some misgivings about the push toward IP cores.