124 karma · joined April 16, 2021
Why not? I understand not wanting to deal with unnecessary complexity as a hobbyist, but you'll find yourself creating far more complexity trying to implement all of this yourself (and vendors certainly don't want to support you in this). Secondly, I think the number of customers for chip vendors who are uncomfortable with setting up an embedded Linux environment, but perfectly confident in routing DDR and PCIe signals is approximately 0.
> What I am trying to point out is that there is a huge market gap.
> i.MX8 is not realtime and the support for running bare metal code is very much non existent.
This isn't quite true and is what I'm trying to get at. Most of these embedded SoCs contain a Cortex-M and a Cortex-A (not all but there are quite a lot). High performance DRAM, external PCIe devices, and large internal caches are fantastic for compute performance but most of the things you want to do with a PCIe device (networking, asynchronous compute) don't require cycle-accurate determinism. Generally there isn't much you need to do with such stringent timing requirements, so you can offload that work to secondary Cortex-M33 core with a shared memory interface to the main core and get the best of both worlds.
I see so many systems trying to take advantage of the impressive compute power of modern MCUs (which is really cool!) but often end up just re-inventing the cooperative multitasking OS, but worse.
[1] https://www.st.com/content/st_com/en/campaigns/stm32v8-high-...
This is so, so much worse than that though, because the code doesn't even do what the AI-hallucinated documentation describes, because as far as I can tell the actual "serial number" is returned by the following line: Ok(Some(format!("{:?}", device.product_id()))) So the "serial number" is actually the USB product id, which generally corresponds to the "model", not even unique per-device. So you didn't even test this with multiple identical flash drives.
> But they will be good helpers for people like me, who can get suggestions, improvements and illustrations just for the price of my 4090 and time to tinker with models.
This I agree with; for someone who may not be as gifted a writer, but still has something interesting to say, generative models could help with that. I just hope that people don’t lean on these models for generating ideas because if that story was any indication, that’ll just lead to a proliferation of boring, soulless works.
Why not? There are plenty of open source RISC-V soft CPUs available for you to run on the same FPGA to benchmark against. If its the architecture which is special it doesn't matter if it competes against top of the line chips, just that it beats out everything comparable. You don't need to prove that your design will beat out a similarly designed chip on advanced silicon, just that your design implemented in the slow FPGA is better at something (not necessarily everything) than a CPU trying to emulate the same behavior. Having the PDKs won't help you much either, since on top of that it will take hundreds of thousands of dollars (minimum) in software costs and teams of people to help fine-tune and simulate such a large design. Doing this without the intention to eventually tape-out that design is a massive waste of resources.
I understand where you're coming from but the point of getting access to those PDKs isn't for rapid prototyping. The value proposition of your design must already be clear before beginning to design for a specific process. If you can't prove that your design has significant advantages that no chip in the next few years can possibly compete with, then there's just no point in attempting to design, synthesize, and simulate it on advanced nodes. That process is a significant investment in itself and if you're unsure enough about the potential benefits that you need to know exactly what it would look like in reality, then it's just too risky to spend the years it will take to get a working chip which may already be outclassed by the time your first chips come off of the line.
> Sure, but I specifically want to research the optimal intermediate point between classical CPU architectures and classical FPGA architectures.
That sounds cool, but this makes it sound like you're a really long way off from considering the specific characteristics of a given process node. Focus on designing an architecture which does something better than current designs can possibly do, such that the value of implementing it in a chip will be unquestionable.
Setting that aside, if you have some revolutionary design for an architecture, that should already be abundantly clear from emulating your designs on FPGA. If you aren’t completely sure (and have evidence to prove) that your design is significantly better than anything that has been made before, you’re not at the stage where you should be thinking about manufacturing a chip with modern hardware. As was said elsewhere, making a chip is a phenomenally capital intense process so if you’re planning on competing with any existing hardware you’re going to need to justify that investment with radical gains, not incremental improvements. If you have an idea which you think could speed up existing hardware, your best bet is to work with/sell IP to companies which already design that hardware since it’s just not worth the investment needed to start a whole new chip company for a potentially 10% better CPU/FPGA.
> We should be striving to make copyright less draconian, not more. Agreed, and I'm not sure why you think forcing GPT and Copilot to respect open licenses will make them illegal instead of more open.