foft

Memories! Back at university I got a G400 and, with the open documentation they released, was able to make a driver for BeOS. It worked but looking back it’s stark how much I have learned since then. One feature I particularly love is a dual head setup app using combo boxes instead of menus!

Th code is still online, in full early 2000s web styling. https://64kib.com/old_foft_site/

The question is what is reasonable. This is more how I work for code and I just tried for a document.

i) Prompt (Human input)

ii) Response (LLM)

iii) For (i=0;i!=n;++i) {

iv) Review/adjust (Human input)

v) Response (LLM(s) - different perspectives) }

vi) Rewrite parts that failed/I am not happy with (Human input).

vii) Optionally repeat from iii.

This tends to get me somewhere I want. For code at least. I made a document with it recently (fairly concise) and still worried I'd missed some AI slop in it. Though there is always human slop if I just made it by myself.

Cutting coffee to just the morning definitely helped me.

My problem now is that if I think of anything vaguely interesting in the evening then my brain refuses to stop thinking about it. That and restless legs.

Evening if my main time for hobby projects so having them lead to disrupted sleep is really annoying. Any tips?

Really awesome. Though I wish they'd do a dense 48B, 60B or 72B.

There seems to be quite a gap between the small ones and the enormous ones these days.

If you put your data in Snowflake then there is a built in AI (ok it’s Claude) that can access the databases. This sidesteps a lot of the issues in that the data is clearly already with Snowflake.

Having used codex a fair bit I find it really struggles with … almost anything. However using the equivalent chat gpt model is fantastic. I guess it’s a matter of focus and being provided with a smaller set of code to tackle.

Yes. If you haven’t yet read it Cory Doctorow’s new book Enshittification is well worth a read. I am still reading it but it certainly explains some of the bad practices by these major advertising/spying giants and the resulting market distortion. We need to up our game as technologists and hold our employers to account.

It was a strange decision to limit the drives. I can see they might want to accredit drives which would give a 'Synology Approved Experience', though outright only support their own was bizarre. I'm very pleased they are reversing this. Aside: Now we just need Apple to do the same and resume support for industry standard expandable memory and storage.

From my perspective it lined up exactly with when I was looking to upgrade. I decided to bite the bullet and go with Duplicati, storing to a European based S3 service. I decided against US cloud providers since the US is looking too politically unstable to put anything important there. It was easy to set up and so far is running well.

If you are interested in FPGA PCIe or PCI cards there are also a lot of Gidel boards available second hand. ProcSpark/ProcStar etc. The official software is proprietary and they often contain multiple FPGA devices so there is again an exercise working out the pinouts etc if you want to simply use them with Quartus. I got one with a massive Stratix IV on.

A Kintel UltraScale+ is quite a prize though, really nice write up.

As a big openscad fan I love the idea of designing circuits with code.

I do wonder though about designing circuits vs designing schematics. I see you have ‘wire down 100’ making it a more visual language than defining the nets. Be interesting to separate the schematic layout from the nets, so rule base schematic layout can then be applied.

I've had great results with Codex, though I found ChatGPT 5 was giving much better results than the existing model. So ended up using that directly instead. So very excited to have the model upgraded in Codex itself.

The main issues with Codex now seem to be the very poor stability (it seems to be down almost 50% of the time) and lack of custom containers. Hoping those get solved soon, particularly the stability.

I also wonder where the price will end up, it currently seems unsustainably cheap.

In Switzerland pretty much all sites have a setting for French, German, Italian and often English. It is very much a multi-language country.

It is great to be able to select individually per site. I often like to use the native French and just drop back to English if its technical language.

I do find that every site has the setting in a different place which is annoying, it would be great to be able to select it in a standard place on the browser.

The worst offenders are the single language per country sites. For example Ebay insists on only using German in Switzerland, which is rather frustrating since I only know English and French so far.

If anyone was interested in the Amiga but has not kept up with recent developments, I suggest looking up the Vampire V4. It is mentioned in the article but I thought I'd add a few more details.

It has a reimplementation of the ECS and AGA chipset. It includes custom extensions to the chipset to 'SAGA' which is an attempt at extending the registers to more modern standards.

It also has a reimplementation of the 680x0 CPU, which is using more modern design techniques. The developer used to work on Power.

Anyway putting it all together its a great system in the vein of the Amiga. Of course it is not as fast as a modern ASIC, being consumer low end FPGA based. Still it is great fun.

Relevant to the Amiga 600? Well there is a standalone version but there is also a version called 'Manticore' that fits into the Amiga 600.

Many people will say you can get similar performance with emulation. This is of course true though, as someone who studied microelectronics, I see the value in real hardware. Both in future potential for making an ASIC and for more precise sub-microsecond level timing.

There is an alternative semi-emulation approach. i.e. emulating the CPU with a raspberry pi and using the rest of the original hardware. This is known as PiStorm and connects the GPIOs from PI onto the 68K to replace the original CPU.

Ouch, if that is the case this is only going to boost the non US suppliers. Has anyone tried lcsc.com? Digikey and mouser are great but if all semiconductors go up 50% that is a problem.

Thom did great work on the Plato stuff. Also be sure to check out his Fujinet work, really nicely done. Ported to many platforms too.

Also read it backwards

It is not just Apple that did this, for example here is an equivalent from Atari: https://www.exxosforum.co.uk/forum/viewtopic.php?f=17&t=1698

Interesting. Reminds me of FlexFS (https://flexfs.io/). I spoke to a very knowledgeable person there when investigating what to use but we ended up using EFS instead.

An annoying feature of EFS is how it scales with amount of storage, so when its empty its very slow. We also started hitting its limits so could not scale our compute workers. Both can be solved by paying for the elastic iops but that is VERY expensive.

Is it possible to use this to make songs for multiple chips at once?

In the pokeymax and sidmax projects I have dual pokey, dual sid, dual ym2149 and a simple dma sample engine available. It would be great to make some songs using all of them for their strengths at the same time.

There are a few improvements that could still be useful:

i) FPGA on a newer process so it can clock higher. For faster 68k in the Amiga core and pentium 1 equivalent speeds in the x86 core.

ii) Faster ARM chip and better ARM-FPGA fabric, opening up hybrid emulation. Currently the ARM-FPGA layer is a real bottleneck and also the ARM core is a little slow.

iii) More spare IO to allow per-system custom io boards.

iv) Built in IO/memory board so they can fit in a nicely designed case rather than the current eyesore.

To do a fab build out and restructuring of this scale clearly they need to spend a lot of money. In that context the numbers from the financial report do not seem that shocking. This all seems to be quite an overreaction in the market. They still have a lot of revenue. They are still dominant in terms of market share. Their CPU products are competitive and reliable despite the process disadvantage. Yes there are issues some percentage of the consumer CPU high end but I'm sure the investigation will be completed and the right thing will be done, they cannot afford the reputational risk of not doing so.

I'm more concerned about how well 18a and beyond is coming on. Also how well is the sales side and client support for this going? I was thinking they were working more with TSMC to learn how this works from a client perspective so they can build something similar.

Regarding AI. Technically speaking isn't the AI hardware largely cut and paste? A much simpler CPU of which there are a few thousand copies. With the expertise they have in RTL design it does not seem that difficult.

That said I do not think that parallel compute of this nature is going to be future of AI, it is too expensive in terms of power. I'm sure a much more efficient structure will be designed in the coming years, e.g. neuromorphic.

The tricky thing here is that as this mostly affects unlocked CPUs it is going to be hard to prove when the fault is from this algorithm vs user/motherboard manufacturer overlocking. Unless there is any internal monitoring with fuses blown. Is there?

As part of the bathtub reliability curve its usual for a large fraction of failures early in life, how much over the usual failure curve are we?

It's still unclear what fraction of CPUs are impacted for both issues. Was oxidation a single fab just for a month and only 5% of produced CPUs? Is the microcode issue in TB 3.0 or TVB, so would only impact the 1[34]900s?

It's also unclear if once degraded it can still reliably work at say 95% peak frequency. In the case of a partial recall it might be worth a discount option if that is the case.

Anyway it's mostly speculation beyond Intel's post on their forum (+Reddit responses), it will be interested to see the next stages which will hopefully clarify some of these. This is just a discussion forum I'm sure the final detailed announcement will the made via their main communication channels.

Why do you discount Gaudi 3? It looks like a very strong offering.

These are still available: https://centuriontech.eu/product/ct63-rev-2022/

There are also expansions for the expansion! People also use the CTPCI to run the desktop on a Radeon 7500. Alternatively there is an FPGA version of the graphics chip called SuperVidel.

Doom was ported to the vanilla falcon making heavy use of the dsp: https://www.leonik.net/dml/sec_bm.py

Cookie permissions and EU advertising options should absolutely be built into the browser, it makes no sense for the user to have permissions on each site individually like this with a different system on each one.

Then the user can centrally review what permissions they gave, revoke them etc.

So no sites should have these kind of approval banners.

We are discussing this on the Atari forums. The person who posted it is a well known software developer who has linked it from his site(2). So far we don't know.

1: Larek, who make Laura. http://atariki.krap.pl/index.php/Larek 2: https://www.arsoft.netstrefa.pl/

I did mean 25% faster, though it was a guesstimate. That was comparing Agilex to Agilex D, not Cyclone V to Agilex D.

FPGA logic in simple terms consists of LUTs (look up tables, used to implement gates) and registers. The LUTs can be chained several times until they connect to a register. Registers are clocked at a frequency.

Now the max frequency is calculated using the maximum time from a register output, through a bunch of LUTs to reach another register. So it depends how long the chain is.

Its more complex than that in reality since there is also the time for the clock to propagate and to route the signals around. Fortunately the software takes care of that.

I don't really know how maximum frequency is specified in the specs, but I guess it'd be something like an ideal register->single LUT->register without much routing.

I'll try to answer this, though my direct experience is only with Cyclone and Max 10.

The Mister uses the Cyclone V 5CSEBA6U23I7 built on TSMC 28nm. It has 110000 logic elements and also a hard ARM.

These are on Intel 7, so there a significant process improvement.

The smallest Agilex D has the same number of logic elements(1) and the largest has 6x as many (2). Note that Agilex tends to be much more expensive than Cyclone.

Realistic maximum clock rates on the Cyclone V are 50-200MHz, depending on the length of the combinational logic chains. For the Agilex I think that it is more like peak 600MHz. So I would guess say 25% faster and say peak 750MHz?

As to fitting all the logic for n64/PS2, I don't know!

1) Comparing these directly is not quite accurate.

2) https://www.intel.com/content/www/us/en/products/docs/progra...

If anyone is Intel in reading this, please can you provide a lead-time for the low end FPGA (e.g. Cyclone V and Max 10) to Mouser and Digikey?

I understand there is an ongoing major chip shortage but it has been over 2 years and historically these were available next day. I'm sure that I'm not the only one waiting for years with finished designs and no information.

I asked Digikey and they told me that Intel do not provide them with good communications, such that they cannot even populate this, never mind to provide a lead time per product. https://www.digikey.ch/en/resources/reports/lead-time-trends