caisley

Wow, awesome thanks for the details! I have once or twice on projects added extra gates as fillers in some 28nm mixed-signal designs for metal layer re-work, but I had no idea that in larger digital teams there was also the practice of adding these types of individual transistor arrays. Super clever!

Modern commercial image sensors are made in process nodes down to 28nm [0], and for visible light have pixels measuring 0.7-1.5 μm. At [0] there a diagram which gives a feel for what technology nodes are available and used for different applications. For example, RF ICs and power management ICs also typically use larger process nodes, and not just for reasons of cost. In fact a larger node, doesn't necessarily even mean older. For example, many technologies allowing better power handling capabilities in integrated circuits have come exclusively to larger nodes.

Regarding node sizes for image sensors, TSMC built a 28nm fab recently for Sony exclusively to make their latest sensors. There was actually a HN post about that a couple years ago [1]. Also, it's important to note that in many applications, the image sensor layer is now actually stacked, with a layer of DRAM (in 45 nm, for example) between, and a ISP (image signal processor) chip on the bottom made in a smaller digital process. You can see an image of that stack up here [2].

[0] https://image-sensors-world.blogspot.com/2020/08/tsmc-report... [1] https://news.ycombinator.com/item?id=24321804 [2] https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-s...

Can I ask how often you guys end up doing gate-level netlist ECOs, instead of re-running synthesis when you're close to a deadline? Also, post-fabrication, if a mistake is found, have you been able to fix it just with a new M1 or M2 mask, instead of paying for a full new mask set?

Hey, I'm not a system-level digital designer, but for government-level initiatives to provide 130nm and 65nm fabs for public benefit, yes it exists!

From the 2025 Free Silicon Conference:

https://wiki.f-si.org/index.php?title=The_Transparent_Refere...

https://wiki.f-si.org/images/e/eb/OpenFab%40FSiC2025.pdf

The initiative started in Germany, where the research institute IHP already provides an open source 130nm PDK and associated foundry, but interest is spreading. Here's the abstract from that talk:

"The European Chips Act aims to double Europe’s share in global semiconductor manufacturing to 20% by 2030. However, most current investments focus on leading-edge nodes and pilot lines, which – while important – are not sufficient to achieve broad capacity scaling. At the same time, demand for mature nodes (≥65 nm) remains strong: over two-thirds of chips in automotive and industrial sectors still rely on nodes ≥90 nm, and this trend is expected to persist through 2030. This contribution introduces the concept of a Transparent Reference Fab – a fully open, scalable semiconductor fabrication model designed to serve as a blueprint for sovereign and trustworthy chip manufacturing in Europe. Unlike traditional pilot lines, the Transparent Reference Fab is production-ready and replicable. It includes open access to process design kits (PDKs), equipment configurations, process recipes, and operational know-how. The fab targets mature nodes, especially 65 nm CMOS, and is intended to be built on existing infrastructure to reduce time-to-market and technical risk. We argue that such a model can significantly multiply Europe’s production capacity by enabling private and public actors to replicate the reference fab across regions. This approach would not only strengthen Europe’s position in strategic semiconductor supply chains but also foster innovation, education, and security through transparency. The paper presents the strategic rationale, technical architecture, and implementation path, positioning the Transparent Reference Fab as a critical instrument for European resilience and competitiveness."

I work in custom CMOS image sensor design, targeting scientific imaging applications like electron microscopes, X-ray microscopy, and detectors for high-energy physics. Our designs aren't that cost sensitive from a unit cost perspective, because we are at most probably making several thousand of the chips. So the cost per chip can effectively range from 10-100$ at this scale, after yield losses. But the fixed costs of engineering and 'mask creation' for process nodes can range from 300k$ for nodes around 180 nm, to over 500k$ for 65nm, and above 1m$ for 28nm and below.

We can save money during initial prototyping, by creating a small test structure as small as 1mmm^2, which reduces the cost of a prototype run to 5k$ - 10k$. Some services that provide this are MOSIS [0] in the US, and Europractice [1] in the EU. But when we go to a full production run, there's no way to get around creating a 'full reticle' design, as image sensors have a physical dimension determined by focal plan size requirement of imaging application. For example, in digital camera, if a sensor is 'full frame' then it obviously has to be 36mm x 24mm, regardless of if the process node would have let you shrink it. And if you make a serious mistake, then you need to do another production run, which means you pay the 300k$ - 1m$ once again.

In terms of the circuit functionality, image sensors require a mixture of analog and digital design, but in this area, even many of the digital circuits are custom designed, rather than relying on foundry-provided 'standard cells' and an automatic place-and-route flow.

[0] https://www.mosis.org/ [1] https://europractice-ic.com/

You're right that most professional designers historically haven't cared about open source tooling. But this is starting to change, largely because of the recent existence of open PDKs and the creation of better open tools like OpenROAD. I am a PhD student working in chip design, and about 90% of my work is done using open tools. You can see an image of one chip here, for example.

https://github.com/kcaisley/frida

Yes, actually 180 nm still represents a sizable amount of the market, in terms of volume! In more niche applications where chips contain lots of analog functionlity, you can still find plenty of designs being done in 180, 130, 110, and 65 nm. Most corporate designs don't disclose this, but I'd venture to guess the majority of integrated circuits in your home are made on these larger "process nodes". I work in 65nm and 130nm, for example. Free to ask if you want to know more!