I work in custom CMOS image sensor design, targeting scientific imaging applications like electron microscopes, X-ray microscopy, and detectors for high-energy physics. Our designs aren't that cost sensitive from a unit cost perspective, because we are at most probably making several thousand of the chips. So the cost per chip can effectively range from 10-100$ at this scale, after yield losses. But the fixed costs of engineering and 'mask creation' for process nodes can range from 300k$ for nodes around 180 nm, to over 500k$ for 65nm, and above 1m$ for 28nm and below.

We can save money during initial prototyping, by creating a small test structure as small as 1mmm^2, which reduces the cost of a prototype run to 5k$ - 10k$. Some services that provide this are MOSIS [0] in the US, and Europractice [1] in the EU. But when we go to a full production run, there's no way to get around creating a 'full reticle' design, as image sensors have a physical dimension determined by focal plan size requirement of imaging application. For example, in digital camera, if a sensor is 'full frame' then it obviously has to be 36mm x 24mm, regardless of if the process node would have let you shrink it. And if you make a serious mistake, then you need to do another production run, which means you pay the 300k$ - 1m$ once again.

In terms of the circuit functionality, image sensors require a mixture of analog and digital design, but in this area, even many of the digital circuits are custom designed, rather than relying on foundry-provided 'standard cells' and an automatic place-and-route flow.

[0] https://www.mosis.org/ [1] https://europractice-ic.com/