Thanks for the feedback! Since our business model is b2b and we are giving away emulation time on some very expensive cloud FPGAs, we figure the automated linkedin auth was fair. With Parallella we had 10K mostly anonymous customers and for a startup that was not great...
Structured ASIC are generally fixed size monolithic chips with metal/via programmablity to control some amount of wiring (hardcopy, easic,..). Modern FPGAs with a mix of har coded blocks (serde, cpus, DSP) connected by NoCs and PL is another example. The front end transistor layers are fixed.
The Zero ASIC platform does "late binding" by wiring together different chiplets (cpu, lm, fpga, serdes,...) in the package. Both approaches are addressing the same problem of flexibility vs performance, but the approaches are very different.
Thanks! Yes, we are focusing on big digital because that's where the big cost problem is. Also, the kind of block based design we are proposing requires a standardized interface. Th standard interface för analog is "a wire".:-). What kind of analog did you have in mind?
This is probably not the place to write a full post-mortem, I will save that for a blog post or something, but here are a few points:
* 2008 was a really bad time to launch a chip startup
* Epiphany predated RISC-V...nobody wants a new ISA
* With <$7M raised in 9 years it was starved, there was no way to turn architeture into a good market fit (this would have required $50-$100M in tapeouts, CPU licensing, IO licensing, sw,sw,sw,,,). This is the problem we are trying to address now.
Epiphany did find some customer end applications (machine vision for example) and the Parallella board shipped in volume. The volumes and number of customers just wasn't big enough. Everybody wants to be the next ARM, Nvidia, but there is only room for 1-2 on earth.
Yeah, I have been struggling with these questions for 25 years and I am not alone.:-) You can always spend $100M and build exactly what you need (eg. 16 RISC-V processors with custom vector extensions and a selection of I/), HBM3, serdes, ...). If you are lucky your with your application fit (cost, power, performance) you could possibly buy a Snapdragon, Xavier, Versal, Agilex. The problem we are addressing is the gap, where you don't have $100M in your pocket and you are constrained by physics (size, weight power) or cost.
Code(RTL, Chisel, C) that can be bundled as a memory mapped IP and turned into a brick integrates really well. The problem is that this reqyuires custom tooling. A full mask set taoeout is going to cost $5M-$10M and take 6 months to complete at a reasonably advanced node.
The challenge with today's FPGAs is that you rarely get exactly what you need. The smalle ones aren't feature complete and the big ones are expensive and power hungry. Lots of questions though, which interface parts are you talking about? The electrical interface (lvds, mipi, cmos, etc), width, resolution, vendor type, or some kind of custom ISP like you would have in a high end camera?
Yes, you are right that pseudo-integrated silicon-photonics is really exciting! The Ayar Labs + Intel FPGA chiplet combo based on AIB is a great example. Packaging is one of the really big challenges, DARPA invested ~$100M to solve this problem with the PIPES program.
It's a 4x4 array of chiplets, the rest is UCIe/IO logic. the ebricks do have some pass throughs, but real IO capability is done through UCIe based chiplets.
As long as the processing is being being done with electrons (CMOS), there will be a pretty big hit for converting back and forth to photons. In package chiplet communication is actually not that inefficient as long as you can put them right next to each other (like on a chip). Intel demonstrated this with AIB. With parallel interfaces, you can get to 0.1-0.5pJ/bit transferred, which is good enough for most.
If an FPGA can get the job done, it's usually the right answer. However FPGA programmability comes with a 25x-100x penalty in terms of area, cost, power, performance compared to application specific devices. Sometimes 100x matters...
Agreed...although not sure if it's any more impressive than automated fabs that churn out nanometer precision transistors with billion transistors chips costing less than a cup of coffee per chip.:-)
The current leading edge processing products moved to chiplets because it was the optimal/only solution from a cost and performance perspecitve. If we assume that reticle sizes will stay roughly similar and process scaling will continue to slow, then it would seem that the future bends further toward chiplets...
The best chips TODAY use chiplets. Check out Epyc, Ponte Vecchio, all high end GPUs and ML accelerators using HBM memory. A chiplet is generally defined as a chip/die with custom interfaces for in package communication.
Yes, here have been a fair number of public DoD studies around the virtues of disaggregation when it comes to security. Minimize the people/things you have to trust (eg. RoT).
As a summary, the last 50 years has achieved smaller, cheaper, faster through monolithic integration Moore's Law). Cost and complexity of design and manufacturing is now making that approach impractical. Disaggregated design and manufacturing through small chiplets is "the next thing". A bit hyperbolic, but it gets to the point ..
From personal experience it's at least 1%. I had a Kickstarter project 10 years ago that had approx 6,000 supporters and 50 were simply awful human beings. Everyone else was ok. Anonymity brings out the worst in some people.
Seems like people are interpreting whatever they want from the original chart by Raja Koduri at the VLSI symposium...plotted with absolute numbers you see that EE enrollment is pretty flat. What has happened is that the number of CS majors has exploded. Kind of makes sense that there SHOULD be 10x programmers for every chip designer? Unless we want the hardware to become the application and for every programmer to be an EE??
I find it kind of weird how many people were offended by our use of the term, supercomputing. The actual specs were on the front page of the kickstarter from day one. Not sure what people were expecting from a $100 SBC? Kind of interesting to note that the Parallella beat out the multi million dollar Thinking Machines of the 1990s in terms of performance...
Hey...this was just me sharing a list of people who have done great work in open source...I don't see why you have to drag Parallella into this...still since you brought it up, Parallella was shipped to 10K customers and used in 200 research publications. What's your bar for success?
Going back to the original H&P texts and RISC philosophy, there is a claim that auto-increment addressing modes is too expensive due to the extra port in the RF + scheduling complexity. For an instruction set that should support embedded in order dual issue processors with math intensive loops, this is arguably a "weird" omission in the base line.
Family plan health insurance premiums on open market is $33K/year in New England (US). With group plans that goes down to $28K/year. A full time employee at $15/hr is $30k/year. The US healthcare system is fundamentally broken...