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Comment by adapteva | Hacker News Reader

This is Andreas Olofsson at ZA, ama...

Not the most interesting question, but: "log in with LinkedIn" as the only option? Really?

I get that you want to generate leads, but giving the least trustworthy social network as there only login option to save 2 seconds pasting a name into the LinkedIn search box isn't a good idea. Many of us are forced to use LinkedIn for career reasons, but try to keep it isolated from everything else, because we remember when it scanned people's contacts without permission and other dodgy behaviour.

Thanks for the feedback! Since our business model is b2b and we are giving away emulation time on some very expensive cloud FPGAs, we figure the automated linkedin auth was fair. With Parallella we had 10K mostly anonymous customers and for a startup that was not great...

I think the GP's issue isn't with the need for a login, it's with the choice of provider.

Do folks prefer FB?

"How sarcastic do you want your answer?"

Yes!

IMO email+password and/or Google sign-in are much better options.

Not really. Yeah, none of the options are great. I'd prefer a nominal payment TBH, but many people would probably not be keen on that (as expensing it could be an issue)

I didn't realise you were giving time away on FPGAs. Probably the best option would be to have a lighter preview that just shows the UX but not simulation, for anonymous users.

Unless you really expect your business to be mostly high-touch sales, giving your potential customers as much information as possible before you demand anything from them is probably the best strategy

Thanks for the feedback. The access mechanism will be adjusted going forward. This was my bad.

That's great to hear

One option I've seen work for a similar requirement is email verification on any corporate address. All you want to know is that they're legitimately connected to a legitimate prospective customer, just make them answer an e-mail on the company's domain.

LinkedIn is a great choice for a login. I had a b2b site, and at first we offered Google, LinkedIn, etc.

Almost everyone used LinkedIn, and of course the profiles were so much more helpful, so we simplified our process and used LinkedIn only. We never had any issue with that, its a great choice

Contextually the most optimal choice.

I guess the interesting question is how this approach compares to FPGAs in terms of cost and performance. Given the functionality of the different chiplets as soft IP, wiring them together and loading the design into an FPGA should be easy enough. So how much more would I have to spend on FPGAs to implement the same functionality as a typical combination of chiplets? How much more to match the performance? Or are there no FPGAs that could fit the functionality or match the performance?

Depending on who you ask, the silicon area overhead of programmable logic FPGA is 25X-100X compared to hard coded logic of an ASIC (at the same node). Very few applications can afford the cost of full platform programmability with large devices costing over $5K.

https://www.digikey.com/en/products/detail/amd/XCVM1802-1MSE...

Does this transalte to if I have a design that I can fit into a $10k FPGA and that can also be implemented with Zero ASIC's chiplets, then I will be able to get a chip in the $100 to $400 range?

A $10k FPGA at Digikey price or a $10k FPGA at the direct from [vendor] purchase price? The former is a medium sized chip, and the latter is a huge one. If you have a volume product, you actually get reasonable pricing from the FPGA vendors.

I would guess if you are considering a semi-ASIC solution like Zero ASIC, then you probably want to build more than a handful of devices, so getting the FPGAs from the vendor would probably be the better comparison. What kind of price difference are we talking about here? The most expensive FPGA I could quickly find on DigiKey is a AMD Virtex UltraScale+ VU57P for $174k in quantity one, what could I realistically expect to pay if I ever needed a thousand of them? Half the price? One tenth?

The price difference for direct, volume purchases of FPGAs is reportedly about 10-50x lower than the unit price on Digikey, but they keep it very secret so they can price gouge you on negotiations. That VU57P likely costs at most $10-15k when purchased directly and in volume.

As a comparison, this fully-built PCIe card with a VU13P FPGA costs $13k at quantity 1: https://www.mouser.com/ProductDetail/BittWare/XUPVV8-0007?qs...

While a single unit of a comparable chip to the one on that card costs $77k on digikey: https://www.digikey.com/en/products/detail/amd/XCVU13P-2FHGC...

VU13s (2104D) can be had from Xilinx for <$1000. New VU35Ps were $700 in modest quantities a year or two ago.

The Bittware CVP-13/XUPVVP product was $5100 new.

Used VU13Ps run $300 in China.

No my bad for not being clear. If all you want is a bunch of LUTs then the high end fpga is the right answer. FPGA today is a lot of other things besides PL (serdes, cpu, DSP, ML, DDR IF...) and some of those features are only available on the bigger FPGAs. FPGA portfolios have man gaps due to the enormous costs of designing each one of those FPGA products.

These Versal chips are around $1500 used in Shenzhen and I am buying $300 VU35P/VU13Ps all day long.

Cool project!

Right now y'all look focused on digital logic somewhere between ASICs and FPGAs.

Any plans for custom chiplets? Custom analog layout might be much cheaper if done MPW or Tiny Tapeout style: design a mere ~100x100um area, then bond it to standardized chiplets for control/power.

Thanks! Yes, we are focusing on big digital because that's where the big cost problem is. Also, the kind of block based design we are proposing requires a standardized interface. Th standard interface för analog is "a wire".:-). What kind of analog did you have in mind?

What's the plan for the protocol on top of UCIe? Any support for CXL? I see you also specifically mention Chisel, so I suppose it's not a total shot in the dark to ask if you're supporting TileLink (ideally TL-C) over UCIe?

Great question! Not ready to announce our protocol yet. Coming soon....

Are there chiplets from other sources? The announcement seems to indicate there is a catalog. But I imagine there are huge barriers to making chiplets from another source / made using a different process / different size and shape and contacts work (maybe? I don't really know)

And another question: The quad core RISC-V chiplet, is that 64 bit? RV64GC? Any other extensions like V, H, ...?

The swappable nature of the chiplet bricks was meant to convey that they are the equivalent of toy plastic blocks. We didn't disclose the standard yet, this will be coming soon.

The RISC-V chiplet a standard RV64GC. The high level spec is at: https://www.zeroasic.com/docs/cpu

My takeaway is that part of the concern is around functional units getting integrated into a SoC that are not 'safe' but might be backdoored or untrustworthy.

Having small IP cores where the source can be verified/audited that can then be snapped together like Lego blocks are very appealing from both a cost savings and supply chain safety standpoint.

Need help hiring RTL/digital IC designers?

I help run FPGAjobs.com and we’ve helped hire folks with that skillset into companies like ZeroASIC.

We could almost certainly help you fill roles like these:

https://www.zeroasic.com/careers/digital-ic-designer

https://www.zeroasic.com/careers/senior-verification-enginee...

Drop us a line at fpga.RTL.jobs@gmail.com if that’s of interest!

What does the software toolchain behind this look like? In particular how are people expected to program the resulting hybrid/heterogenous architecture.

Each chiplet comes with its own tool chain. The FPGA has a full RTL2BITS tool chain, the CPU is supported by standard RISC-V tools, and the ML chiplet will have a typical ML programming flow. The full system parallel heterogeneous programming challenge is something the whole industry is grappling with. It's an unsolved problem. DARPA started a program on this topic in 2020 called PAPPA.

The manycore emulation demo kind of hints at where we are going...more information to follow in the next few months.

https://www.zeroasic.com/emulation

How does this differ from Structured ASICs?

Structured ASIC are generally fixed size monolithic chips with metal/via programmablity to control some amount of wiring (hardcopy, easic,..). Modern FPGAs with a mix of har coded blocks (serde, cpus, DSP) connected by NoCs and PL is another example. The front end transistor layers are fixed.

The Zero ASIC platform does "late binding" by wiring together different chiplets (cpu, lm, fpga, serdes,...) in the package. Both approaches are addressing the same problem of flexibility vs performance, but the approaches are very different.

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