U.S. focuses on invigorating ‘chiplets’ to stay cutting-edge in tech
nytimes.com
nytimes.com
And is it really impossible to sneak an antenna into chiplet?
Sub in chiplets for motes. Also antennae are not the only side channel attack out there.
For example, you want to use the fancy new process node that's only available from SketchySemi in some other country. They're happy to do business with you, but you're worried about hardware trojans.
Chiplets help isolate the untrusted component so you can focus your scrutiny on its i/o.
SketchySemi could put antennas inside the chiplet they sell to you, but you have freedom to orient the chiplet however you want, wrap it in shielding, throttle its power, etc.
TEMPEST shielding is also a thing:
I'm curious to what extent software built in this isolated silos scheme actually works, best guess is it's OK but slow and expensive to build. Same idea might apply here, i.e. it's a way to make hardware take longer to put together.
Is there such a thing?
Will this eventually give me more FPS in cawadooty?
1) the yield is better for a small die. For a given density of defect, a big chip will have a higher probability to have a defect than a small one. Basic example: you use 4 chips instead of one, and one defect that would kill the big chip will only kill one of four of the small chips. It's more subtle than this, there are simulators on the web to see the impact of size on cost for those interested;
2) parts of the chip can use cheaper nodes. For example the I/Os not only can use less advanced and cheaper nodes, but those nodes have often better support for analog IPs.
On the flip side, communications that were internal in the big monolithic die now must cross those small dies boundaries. And communications is expensive: you would certainly not want to handle this through a PCB. Instead, more local short range interconnects are used that are much more power efficient than a PCB interconnect (but not as good as in die). These require sophisticated packaging, which adds to the cost. Still for complex chips the net effect is positive, see what AMD did (with Intel now following).
I could believe they're more vulnerable to mechanical damage. Also seems possible that the thermal expansion introducing mechanical stresses is more of a problem. I suppose we won't really know for a while yet.
I saw a demo from Kodak once where they printed a fiber optic backed motherboard and it was lightning fast even when they increased distance. No clue what the heck happened to that tech but I do recall one of the folks giving a lengthy explanation about how fiber optics could replace some of the metal used in cpus because they could make microscopic glass
Edit: turns out I was on to something with this, there is work being done on this exact problem[0]. I still wonder WTF happened with that Kodak tech though
[0]: https://spectrum.ieee.org/amp/optical-interconnects-26589434...
Also the amount of heat in a given area is rising. We need to spread it out or find some really innovative ways of dumping the heat.
I suspect as time goes on, prices per transistor will become absurdly cheap but you'll need to do things like have redundant hardware running half the time to get rid of the heat.
However I fully expect this to be the future. The performance per $ is what really matters to the bean counters, and us software engineers will just have to write better software to work around it, perhaps with something like NUMA-aware scheduling that understands chiplets.
Microservices are supposed to improve testability, reduce complexity, etc: it is an organizational choice. Chiplets add complexity: silicon interposer, tougher packaging, NUMA, etc: it's an engineering choice with a tradeoff for better yield, chips reaching maximum reticle size, etc
trust boundaries
open vs. closed IP
old vs. new processes
onshore vs. offshore
supply chain resilienceConsider AMD's approach. They use multiple CPU dies in a single package to build very high core count systems that would previously have required multiple sockets. Bringing these into one package can make communication more energy-efficient and faster, as well as simplifying other aspects of the system. They also use different processes for different dies. The "IO die" is fabricated on a slightly old process as it is not performance-critical while the best process is reserved for building cores.