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_quarks_on Show HN: A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA

The neoTRNG provides a tiny (less than 70 LUTs) true random number generator for any FPGA. No device-specifc macros, libraries or attributes are used at all.

The quality of the generated random numbers has been verified with the "dieharder" random number test suite.

_quarks_on Show HN: A Technolgy-Agnostic Physical Unclonable Function (PUF) for Any FPGA

This is a tiny (less than 200 LUTs) Physical Unclonable Function hardware module for FPGAs. It provides a unique 96-bit "fingerprint" that can be used for security-related applications like key-generation or authentication.

The fingerprint is defined by the FPGA's semiconductor characteristics. The same bitstream will lead to different fingerprints when programmed to different FPGAs of the same type.

The whole design is written in platform-independent VHDL. No device-specific macros, primitives or attributes are used at all so the design can be implemented on any FPGA (tested on Intel, Lattice and (in-progress) Xilinx). (the "platform-agnostic" concept/technique was taken from the NEPORV32 TRNG -> https://github.com/stnolting/neorv32)

A few bits of the raw fingerprint from the module are quite noisy, so a software post-processing is required. I have implemented a simple "averaging" mechanism here. Error correction codes might be much better - but I am still fighting with the theory behind them ;)

I have tested the design on several FPGAs with promising results (see GitHub page). However, I still need to do more long-time testing to ensure stability of the fingerprint.

Feedback is highly appreciated!

_quarks_on A generic VHDL touch controller – add capacitive buttons to any FPGA

You cannot really maintain that. The controller has to adapt. That is what the two reset signals are for. The synchronous one can be trigger by application logic (for example some sort of timer) to re-calibrate the touch controller.

_quarks_on NEORV32: A customizable RISC-V SoC

The core provides (depending on configuration) ~0.9 coremarks per MHz.

The base core has 32 GPIOs (32xinput + 32xoutput) and no DMA. If you need a DMA or more GPIOs you can attach them to the Wishbone/Axi interface.

_quarks_on Open-source soft-core RISC-V SoC with gdb support

I thought so, too. I have read about the Lattice MACH-NX having a secure enclave based on a RISC-V CPU, but it seems like this is just a soft-core CPU as well.

_quarks_on Open-source soft-core RISC-V SoC with gdb support

It is hard to compare two RISC-V cores if they do not have similar configuration options. For example: what kind of ISA extensions, supported traps, custom extensions, CSRs, etc. does VexRiscv "SmallAndProductive" configuration include?

I like that it is written in VHDL and provides an all-in-one package: cpu, soc and software

_quarks_on Open-source soft-core RISC-V SoC with gdb support

Full-scale RISC-V soft-core microcontroller SoC with on-chip debugger compatible to openocd and GNU gdb

_quarks_on The NEORV32 RISC-V soft-core microcontroller

A size-optimized and highly customizable soft-core micorcontroller based on a rv32[i/e][m][a][c][b][Zfinx][Zicsr][Zifencei] +[u][PMP][HPM] CPU.

The SoC includes internal memories/caches together with common peripherals like timers, serial interfaces, Wishbone/AXI-connectivity, GPIO/PWM, a TRNG and even a dedicated Neopixel LED interface.

Written in platform-independent VHDL

Tested on Lattice, Intel and Xilinx FPGAs

Full-blown data sheet

Doxagen-based documentation of the software-framework (including FreeRTOS port)

BSD 3-clause license