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134 karma · joined March 28, 2021

submissions comments

A Transparent Wishbone-to-SPI Bridge Supporting Execute-in-Place (XIP)

github.com·17 pts·_quarks_·

Show HN: A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA

github.com·5 pts·_quarks_·

Show HN: A Technolgy-Agnostic Physical Unclonable Function (PUF) for Any FPGA

github.com·1 pts·_quarks_·

A Dive into the Sipeed Tang FPGA

justanotherelectronicsblog.com·22 pts·_quarks_·

Zephyr OS adds support for technology-agnostic soft-core RISC-V SoC

docs.zephyrproject.org·4 pts·_quarks_·

A generic VHDL touch controller – add capacitive buttons to any FPGA

github.com·77 pts·_quarks_·

Custom RISC-V Processor Built in VHDL

hackaday.com·3 pts·_quarks_·

NEORV32: A customizable RISC-V SoC

blog.adafruit.com·73 pts·_quarks_·

Open-source soft-core RISC-V SoC with gdb support

github.com·94 pts·_quarks_·

Open-source RISC-V soft-core NEORV32 adds on-chip debugger support

github.com·2 pts·_quarks_·

The NEORV32 RISC-V soft-core microcontroller

github.com·1 pts·_quarks_·