NEORV32: A customizable RISC-V SoC | Hacker News Reader

NEORV32: A customizable RISC-V SoC

blog.adafruit.com

73 points_quarks_10 comments

Why not link to the GitHub?`

Also the Documentation

https://stnolting.github.io/neorv32/

This is absolutely one of the best documented free hardware projects that I have ever seen. Most company documentation is worse by far.

Wow, that is good documentation. And it's VHDL too (which I prefer to Verilog).

IMO, VHDL and Verilog are both outstandingly terrible. There are tons of good options that compile from another language to VHDL/Verilog, such as Clash, Chisel, and nmigen. I cannot recommend strongly enough to use any of those over VHDL or Verilog.

My personal favorite is Clash - it’s unusual in that it actually compiles the host language (a subset of Haskell) into VHDL/Verilog, rather than simply providing a library which you can use to create circuit objects. This means you can compile your hardware and run it like a normal program, or include it as a library, or whatever. Very nice for testing. You can also use arbitrary libraries as long as you don’t use anything that falls outside the compilable subset.

I'm kind of torn on the alternative HDLs. The HDL code they generate is often not very readable. When you're simulating you're effectively debugging that generated code. Generate statements in VHDL/System Verilog can often cover some of the use cases. Mostly I find them useful for testbench generation - that seems to be where things like Cocotb really shine.

For Chisel, the most popular tester Treadle has VCD dumps built in. That way you can do your behavioral debugging directly with the source. Of course, for anything involving timing etc you'll have to go with the relevant vendors' tools, which is typically Verilog/VHDL.

It's not hard to do better than typical hardware vendor documentation.

I ran RV32 core on FPGA, it was useful but painfully slow.

Does it really have only 32 GPIO? No DMA?

The core provides (depending on configuration) ~0.9 coremarks per MHz.

The base core has 32 GPIOs (32xinput + 32xoutput) and no DMA. If you need a DMA or more GPIOs you can attach them to the Wishbone/Axi interface.

Where or when can we get these chips/boards?

The github readme lists at least 3 FPGA boards you can use.

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