These languages are fun. "Look ma, no verilog!" But the underlying problem with all of these DSLs is the fact that the EDA[0] industry interoperates on verilog. Period. Worse, at some point in the design cycle, post-synthesized gate-level verilog becomes the codebase.
No upstream verilog changes are allowed because it can be difficult to get a precise edit (e.g. 2-input NAND into a 2-input AOI by changing a verilog function) and you just don't have 3 weeks of runtime to go from verilog to GDSII again. Or you want to make a metal-only respin that only changes one $0.xM mask layer and requires 8 weeks of fab time instead of changing multiple metal layers including the base and needs 16 weeks and a $xM payment.
Programming language design is quite rich because they used to cross-compile to C, and now they generally generate LLVM IR. It doesn't matter what the bug is in the final binary; you're not going to hex edit the binary like you would with a single metal layer of a 300mm wafer. You're just going to recompile and it generally doesn't matter if one machine instruction changes or 1M do because unlike verilog, not even GHC needs 3w to compile a program.
source: I've been on chip design teams for 2 decades and finally gave up on fighting verilog.
[0]: Electronic Design Automation. Synopsys, Cadence, Siemens, Ansys, etc.