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veriloggedon Capturing a UART Design in MyHDL and Testing It in an FPGA

What's your opinion on PSHDL and Chisel? They try to solve these problems in very different ways. PSHDL can interact with standard VHDL code. Chisel can generate Verilog and C++-based cycle-accurate software simulators.

https://pshdl.org/

https://chisel.eecs.berkeley.edu/