razer6

1,599 karma · joined March 3, 2016

razer6··on The risk of RISC-V: What's going on at SiFive?

There is a successor called Noel-V: https://www.gaisler.com/index.php/products/processors/noel-v

razer6··on BOOM v2: an open-source out-of-order RISC-V core

There is the PULP project (http://www.pulp-platform.org/) by ETH Zurich and University of Bologna with different open-source RISCV cores written in (System) Verilog.

razer6··on 6th RISC-V Workshop Proceedings

Not exactly true. There exist different tapeouts in academia (e.g. http://asic.ethz.ch/2016/Patronus.html or http://asic.ethz.ch/2015/Imperio.html) as well as in industry (which are not public).

razer6··on Introducing paid subscriptions on GitLab.com

CI is still free. For public repos nothing changes related to CI. For private repos, the build time is limited. However, you always can use a custom runner for your private repo to have unlimited minutes.

razer6··on RISC-V Offers Simple, Modular ISA

You can always start playing around with PULPino on a FPGA :)

razer6··on RISC-V Offers Simple, Modular ISA

You can start playing on FPGAs. There are prebuilt Xilinx images for PULPino :)

razer6··on RISC-V Offers Simple, Modular ISA

You may want to try PULPino: http://www.pulp-platform.org/

razer6··on Open-Source Processor Core Ready for IoT

The lowRISC team (http://www.lowrisc.org/) aims to develop a Linux capable open source SoC based on RISC-V. They want to use the PULPino RI5CY for their minion cores.

razer6··on Open-Source Processor Core Ready for IoT

The PULP team added a release plan how they proceed with open source: http://www.pulp-platform.org/release-plan/

razer6··on PULPino – An open-source microcontroller system based on RISC-V

* f32c https://github.com/f32c/f32c

razer6··on PULPino – An open-source microcontroller system based on RISC-V

Fabrication yes. But no sale yet. PULPino is taped-out on the Imperio ASIC for engineering samples.