Those who recognize this will be at peace since they understand the soul of bureaucracy.
189 karma · joined August 7, 2021
Those who recognize this will be at peace since they understand the soul of bureaucracy.
https://prabhuullagaddi.substack.com/p/simulation-of-keyword...
I use this a SSG (Static Site Generator). This is helpful since I don't need to learn one more SSG since I am already aware of Python and little bit of html/css.
Given the limitations, still I feel, using GNU/Linux is better than Windows for most use cases like surfing web, Terminals, LibreOffice, SW development etc...
This adage can be seen in the Neitz-sche's statement - "exploitation is a basic function of life".
Only solution to all this is: Think how would we live if such entities did not exist. Then develop necessary skills and use them in daily life.
Even C functions are pre-fix. [function_name arg1, arg2 ...] If schools were teaching pre-fix, we would be in better position to appreciate Intel syntax.
Higher maths uses pre-fix, for example: y=f(x) unfortenately, above line is not pure prefix... = y f(x) would be pure pre-fix.
So, I do not use 90 degree turns for this reason, if not for the EMI reason.
https://en.wikipedia.org/wiki/Unified_Payments_Interface
In December 2019, noting the success of UPI, Google suggested the US Federal Reserve Board to follow UPI as example in developing FedNow,[22] a real-time payment system for United States.[23]
It has cache facility to speed up re-builds. scons --implicit-cache I heard people say, Scons is slow, but it need not be if we use cache facility.
Some people say Meson (https://mesonbuild.com/) would be its successor, but I use scons for building my C/Python files. (ex: Python to .mpy files, asciidoc to pdf, html etc)
Seems, reading the book on the browser is the only option, that is how I did it since many weeks.
Yet I posted this because- - Book is really good for learning RISC-V Assembly.
- There are plenty other RISC-V simulators. Use what you like. For learning each instruction one by one, I like the following sim. https://www.cs.cornell.edu/courses/cs3410/2019sp/riscv/inter...
or read more here: https://medium.com/swlh/risc-v-assembly-for-beginners-387c6c...
- RISC-V has very small number of instructions (less than 100, the integer version has less than 50), compare this to ARM, X86 etc. By the way, word "REDUCED" in RISC does not mean less number of instructions in ISA. Rather it means, each instruction has significantly "REDUCED" functionality such that, it can be easily executed in single clock cycle, can be implemented with less gates, easy to build pipelines, easy to add super scalar units etc. overall simplicity is main goal to get multitude of benefits. Yet, I see, even ChatGPT told me that other way around until I pointed that ARM ISA (being RISC) has significantly higher number of instructions compared some other CISCs. I guess why it failed to understand a fundamental concept of computer architecture that it is running on. May be, corpus of text it trained. It is a irony, yet we are told, AI can think (I still use AI!)
However, it told one thing very correctly: All RISC-V have Load-store model, where entire ISA can be devided into 2 parts: First part, instructions that purely work on cpu registers without ever making memory access. And second part, where instructions that only access the memory. This is fundamentally load store architecture which is one of the must part of RISC-V. But load-store can also be used in CISC.
Correct me if I am wrong here.
Last but not least: If I can turn time back and learn programming language, I would learn RISC-V assembly, ( not C or Python or JavaScript ...). In that sense, I am learning RISC-V and sharing it to others.