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RISC-V Assembly Programming

riscv-programming.org

97 pointsprabhu-yu21 comments

From the Glossary:

    binary digit is a digit that may assume one of two values: “0” (zero) or “1” (one)
    10, 11, 14

Those examples of binary numbers are just terrible.

I hate to be the obnoxious guy that explains jokes, but the 10,11,14 are pages where the concept is explained. This made me chuckle.

Thanks, I’ve glossed over the word “glossary”.

That really didn't need examples, it defines binary digits as either 1 or 0, no need for further elaboration

Aren't we all waiting for that ONE Intel/AMD level competitive RISC-V processor. With full PCIe Lanes, Memory Controllers, integrated Graphics and so on....

RISC-V is already gaining steam in embedded systems. Apple, for one, is replacing some embedded ARM cores in their products with RISC-V cores.

As others have pointed out, we've got SBCs aplenty, and the first laptop systems are coming out later this year.

I get that as humans using computers we're eager for a RISC-V system that matches performance of other modern processors, but it's naïve to think that it isn't a viable platform until it competes with an Ryzen 7.

We are, RISC-V is a really cool architecture, can be complex enough to run full desktop Linux distributions, simple enough for a single person to make a RISC-V processor

Milk-V pioneer, and Intel horse creek are kinda like that, I think.

I'm personally waiting for the second wave of those types of releases, with hopefully rvv 1.0.

There's another good introduction to RISC-V and assembly book here: https://github.com/johnwinans/rvalp It's still a WIP but the TeX sources and processed PDFs are available.

"Free" book. Actually a really annoying (to the point of unusable) dynamic-loading paginated html page. Surely nobody'd ever want to learn anything (much less RISC-V assembly) like this.

The PDF itself nowhere to be found, although I expect one will be generated by hackish means and uploaded somewhere soon. (edit: z-library and Anna's both have it as PDF)

The simulator is similarly locked behind the webbrowser, but seems to be at least based on an open source one[0]. Whether it has been modified is unclear.

0. https://github.com/antoniocgj/RISC-V-ALE

I understand you. I had same thoughts.

Yet I posted this because- - Book is really good for learning RISC-V Assembly.

- There are plenty other RISC-V simulators. Use what you like. For learning each instruction one by one, I like the following sim. https://www.cs.cornell.edu/courses/cs3410/2019sp/riscv/inter...

- RISC-V has very small number of instructions (less than 100, the integer version has less than 50), compare this to ARM, X86 etc. By the way, word "REDUCED" in RISC does not mean less number of instructions in ISA. Rather it means, each instruction has significantly "REDUCED" functionality such that, it can be easily executed in single clock cycle, can be implemented with less gates, easy to build pipelines, easy to add super scalar units etc. overall simplicity is main goal to get multitude of benefits. Yet, I see, even ChatGPT told me that other way around until I pointed that ARM ISA (being RISC) has significantly higher number of instructions compared some other CISCs. I guess why it failed to understand a fundamental concept of computer architecture that it is running on. May be, corpus of text it trained. It is a irony, yet we are told, AI can think (I still use AI!)

However, it told one thing very correctly: All RISC-V have Load-store model, where entire ISA can be devided into 2 parts: First part, instructions that purely work on cpu registers without ever making memory access. And second part, where instructions that only access the memory. This is fundamentally load store architecture which is one of the must part of RISC-V. But load-store can also be used in CISC.

Correct me if I am wrong here.

Last but not least: If I can turn time back and learn programming language, I would learn RISC-V assembly, ( not C or Python or JavaScript ...). In that sense, I am learning RISC-V and sharing it to others.

I don’t think that’s a good way to measure whether AI thinks or not. Many humans might make that mistake but you wouldn’t then come to the conclusion that that person can’t think

>Book is really good from learning RISC-V Assembly.

I'd suggest the spec or the "RISC-V Reader" book instead, particularly if you already know any other assembly language.

Just print to PDF. Somewhat annoying but whatever. For me the correct scale seems to be "page width" or 75%.

This doesn't work for me, most pages are blank.

Did you try print to pdf in browser?

I got the same result: all pages after the Foreword at page 4 and except a couple towards the end are blank. I tried printing to PDF, then the Save to PDF function of the FoxyTab Firefox extension; I also tried to save it a a single file using the SingleFileZ extension that saves pages and data using a compressed single file (thus no conversion to PDF) which is directly readable by Firefox. No way, always blank pages after the Foreword. Not sure if that's a protection scheme or a bad conversion from pdf, but to me being forced to be online and use a browser to read a book kills any interest.

About protection: I see book is in github as a public repo. I will try to print with my pdf tools. Please give me some time.

Just link the repo?

With the right tools, it can likely be used to compile the book into a proper PDF, rather than using print workarounds.

Repo Link: https://github.com/eborin/riscv-programming I may be wrong. I am not able to see the content of the book. (I thought, above repo has the content.). More ever, I see copyright notice in the book. So, it is open for reading purpose only.

Seems, reading the book on the browser is the only option, that is how I did it since many weeks.

This is the generated book. Pretty sad.

Fortunately, as mentioned in my post at the root level, there's PDFs available in the usual archivist libraries.

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