6,420 karma · joined January 15, 2015
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Oh good, now all that garbage is being synced across machines. Lovely.
- %userprofile%\.vscode -> %appdata%\vscode
- %CSIDL_MYDOCUMENTS%\Call of Duty -> %userprofile%\Saved Games\Call of Duty
Because my documents and home directories filling up with a bunch of garbage which has a designated place on the filesystem filled me with impotent rage. I scaffolded out a project to write a filter driver in rust, read through the minifilter documentation, realized how much work it was going to be, and gave up.
I have made my peace with the fact that a windows system is just going to be filled with garbage.
Incredible.
If you have a pretty normal use case the Bins (decodebin, transcodebin, playbin) make that pretty easy. If you have a more complex use case the flexibility of the design makes it possible.
> This request requires up to three timer clock cycles. If the selected timer is working at slow clock, the request could take longer.
Let's ignore the weirdly ambiguous second sentence and say for pedagogical purposes it takes up to three timer clock cycles full stop. Timer clock cycles aren't CPU clock cycles, so we can't just do `nop; nop; nop;`. How do we wait three timer clock cycles? Well a timer register read is handled by the timer peripheral which runs at the timer clock, so reading (or writing) a timer register will take until at least the end of the next timer clock.
This is a very common pattern when dealing with memory mapped peripheral registers.
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I'm making some reasonable assumptions about how the clock peripheral works. I haven't actually dug into the Marvell documentation.
I’m sure some will disagree with this but most PC gamers I talk to want to be at 90FPS minimum. I’d assume if you’re spending $1600+ on a GPU you’re pretty particular about your experience.
[0]: https://github.com/rust-lang/rust/blob/master/tests/codegen/...
[1]: https://github.com/rust-lang/rust/blob/d4025ee454169fbd22f57...
1. There are dummy transistors included in the design for various manufacturing reasons, and there's no standard as to whether those are included in the numbers.
2. SRAM cells in particular are highly optimized and the amount of SRAM (e.g. cache memory) on the chip versus logic will have a big influence on the transistor density.
He said he's still asking around the engineering team for a more complete explanation but that's the supposition.
And yeah the quality of customer service we’ve gotten from three different business providers has been exceptional. It’s crazy to have actual engineers you can call who know what’s going on. You get what you pay for.
If we use the numbers from the preview:
| |Arc A770|Arc B580|RTX 4060|
|--------|--------|--------|--------|
|Process |N6 |N5 |N5 |
|Die Size|406mm^2 |272mm^2 |159mm^2 |
|Trans. |21.7B |19.6B |18.9B |
|Mem Bus |256 bit |192 bit |128 bit |
|TDP |225W |190W |115W |
|~Perf |90% |110% |100% |
In terms of performance per die area it's a big improvement over A770 but still far behind Nvidia. It's interesting that the transistor density is so much lower than the 4060 despite having the same (or at least similar) process node. Speculating about why that may be:- Nvidia has better layout. - Intel is using higher performance (larger) transistor libraries or layout in order to hit the higher boost frequencies (2800 vs 2460). - Wider bus interface takes up more space. - The B580 may have 1 render slice and 64-bits of memory bus disabled, and they're not including those transistors in the count, but they still take up area.
[0]: https://www.techpowerup.com/review/intel-arc-b580-battlemage...
Anyway, whatever woes GloFo is facing you can’t blame them on AMD. They had an exclusivity deal for a decade which only got broken when it was no longer tenable and AMD still buys a ton of their wafers. I suppose AMD may have bought more wafers if their products didn’t suck for most of that time but it had nothing to do with shifting production to TSMC which only happened after GloFo gave up.
The CISA does this type of thing all the time. Here is an example just from their recent news releases in the past week: https://www.cisa.gov/news-events/alerts/2024/11/21/cisa-rele...
The CISA offers to assist infrastructure providers in a number of ways: https://www.cisa.gov/resources-tools/services/assist-visits Presumably the NRWA could have asked the CISA for help with this initiative.
The CISA has 3,000 employees and a budget of $3B, which is a lot, but not enough where they can be involved in everything. For reference there are 12,500 utility scale power plants and 148,000 public water systems in the United States. The scale of the problem means they must be mostly an advisory organization, where most of the work gets done by people at the infrastructure organizations or, sure, volunteers.
Now, I’m not saying that the CISA is doing a good job, I genuinely have no idea. Determining that would take a lot of knowledge, probably insider knowledge, and weighing what they’re doing against what resources they have available. But them not being involved in some random project that showed up in your newsfeed doesn’t mean they have severely failed.
I also had (a different) issue with SPI communication (the W6100 uses a little different protocol).
I still couldn’t get any Ethernet packets to send/receive with a real machine, so I did basically the same debugging step: bought an off the shelf W6100 dev board and planned to use their arduino library to compare against. That’s where I left that project.