I'll have to look at this for my relay computer, which is similar in some ways to PDP-8 (but has even less memory).
http://relaysbc.sourceforge.net/
But how do any PDP-8 compilers deal with the paged memory system? I mean one luxury of 6502 is PC-relative branches. On the PDP-8, jumps reach only within the current page.
PC relative is nicer because it has this property: shortening a branch is guaranteed not to make other branches longer. So you can optimize branches using a relaxing algorithm: you repeatedly try to shorten every branch in the code. If any were shortened, you repeat the whole process since prior shortenings may have made other branches shortenable.
On the PDP-8 this rule does not hold, shortening a branch can cause other branches to become longer, because the different code position may push the target into a different page.
PIC microcontrollers also have this problem.. but on the PDP-8 the problem is worse in that the page sizes are smaller.
Hmm, well here is one algorithm: in one phase shorten branches, but do not change the code size (insert NOPs to make the long branch the same size as the short branch). So this will increase performance, but not reduce code size. In second phase try to delete the NOPs. Only delete a NOP if it will not break any branch. This is not optimal, but maybe good enough..
Ugh, it's even worse because long branches on the PDP-8 involve indirect addressing, where the long address has to fit in the current page. Wow even PIC is nicer..
Anyway for Small-C, they talk about these issues here:
https://so-much-stuff.com/pdp8/C/Assembler.php