IIRC TSMC's 135MBit 5nm example is 79.8mm^2, although that's got other logic.
In the abstract, a 0.021 square-micrometer-per-bit size [1] says you'd need about 21mm^2 for a gigabit (base 10) of 5nm SRAM, without other logic.
Micron claimed 0.315Gb/mm^2 on their 14nm process, [2] so somewhere between a factor of 6 and 7.
That said, my understanding is that there is some sort of wall around 10nm, where we can't really make smaller capacitors and thus the limitation on things. (This may have changed since I last was aware however.)
(There is also the way than 'nm' works these days... but I'm not qualified to speak on that)
Also, AFAIK SRAM is still broadly speaking more power hungry than DRAM (I may be completely out of date on this though...)
[1] - https://fuse.wikichip.org/news/3398/tsmc-details-5-nm/
[2] - https://semiengineering.com/micron-d1%CE%B1-the-most-advance...