gsmadhusudan

This is one of the raging debates within the RISC-V group and elsewhere. Is weak memory semantics really worth it or can x86 style TSO be implemented optimally.Lot of anecdotal evidence but no conclusive experiment. As part of our work we hope to try multiple memory models in our I-class and get some definitive answers.RISC-V by the way supports ARM/PPC style weak memory model or optionally an x86 style TSO.

The Risc-V ISA is far more modular and extensible. Also we needed the 128 bit support for our NVM storage research and single address space OS work. No MMU, T-ISA based security, VIVT caches. Other govt projects do have ARM licenses, we chose not to go that way for purely technical reasons. Our lab does have academic collaboration with ARM.

It is not charity. Computing has become a public infrastructure like roads and water supply. So it is by nature a public good. The underlying foundation has to be based on the principle of the commons and not controlled by one entity. In processors just an ISA will not do, there needs to be open and state of the art implementations at every segment. That is the goal of Shakti. For example We also have GPS/NAVIC receivers and LTE modems in the works. Our comm research groups are far large than our compute groups, so no manpower shortage. They in fact came up with a short lived WiMax like standard which saw wide deployment via IIT incubated startups.

Yes, we are also collaborating with them. The HW is the simpler problem to solve. SW life-cycle for creating tags, embedding them in the code and ensuring that teh binary has not been tampered is the challenge and to ensure portable tag semantics. We have a dedicated security group working on it. Unlike US universities we have carte blanche for hiring faculty and scholarships for MS/PhD. Funding is not the issue, getting good faculty and students is ! Some of you should head over here for an MS or PhD.

I am not sure where we have indicated that the focus is only on IoT class cores. The E and C class are aimed at that segment and this segment probably will account for the vast majority of cores shipped. So they are the first ones to be shipped. The I class for example, an early version which is on-line will be a full OO core - quad issue - dual threaded.Server, HPC and vector based cores are equally important for us. The core road-map is clearly outlined on the codeline.

Yes, we will update the C Class next month since our private line has a lot of foundry specific code that needs to be removed. The I class needs more work but the design is in place. It will also move to quad issue and would be a Cortex A72/75 class core. More importantly the basic slow IPs, UART, I2C, quad/Octal SPI, SDRAM controller, JTAG, DMA, PLIC will be FPGA and silicon proven and production quality. Will be very useful to other developers (non RISC-V also) as would the AXI bus.

Everything has to be monkey proofed, going to the refreshment room when a monkey gang is around is like running the gauntlet ! We are talking really aggressive simians. But totally worth it, I could spend hours watching the monkeys. Surprised that we do not have a simian cognition research group on campus. The slender loris are really beautiful too but I have never seen them.

http://www.thehindubusinessline.com/multimedia/dynamic/02331...

Now if I could get the monkeys to learn bluespec ...

That is what the team is spending is spending its time on, PPA optimization so that we have a good idea how far we can go. Iterating with as many process corners as possible to get the right compromise.. But we have to be careful, it is a new low power process node. The backend team is a very accomplished team from a leading VLSI design services entity who are helping us out. That team is also doing a 7nm tapeout simultaneously for a commercial customer, so they know how to route a chip ! Take apart a flagship mobile phone and you will see their handiwork. It is not a bunch of students trying their hand at PnR. Our team sticks to the architecture, design, coding and verification since these are our core strengths. We also get our work audited by external entities. Bottom line, we are as professional and process oriented as any commercial outfit.

Rust support is getting better. Our Rust OS is lower priority but it is needed for our tagged ISA support since we need language extensions to add security semantics to pointers. Also Rust is a much safer language. We need all this since safety critical systems is a key Shakti target.

That is a compliment I will gladly accept. Look I come from a long line of theologians and philosophers dating back a millenia plus . The Indian ethos of not charging for knowledge has prevailed this long and I am not about to break a tradition ! It is not that we are averse to the ways of capitalism, folks from my family have funded and run some of the biggest tech startups in the valley. I have also run startups earlier and am incubating a couple now. So I know what free money implies. But the core ethos of Shakti is openness and that will never change. See my other effort - finlibre.org. Open source in banking and insurance.

I am very much interested in the maker community and would certainly do whatever it takes to engage that segment. Doc is th Achilles heel of efforts like ours and we intend to address that. Our code for example is extremely well commented and structured.We have 20 character variable names !We work with Xilinx, Altera and Microsemi and will target low cost dev boards but more importantly also tapeout ASICs for arduino boards.But first need to focus on our tapeouts.

http://iglc2018.com/images/iit/4.jpg https://qph.ec.quoracdn.net/main-qimg-2200d147343aa841a43a07... http://2.bp.blogspot.com/_OgX4b2N9a8E/S7OVv7jxhmI/AAAAAAAAAh... http://www.mbaskool.com/2013_images/photography/landscape_na...

We are one of the last refuges of the endangered black buck. The spotted deer and bonnet macaques are more common in India. Odd that a university campus in the middle of a city is a refuge. The pic is that of an albino black buck, an even rarer mutant.

I got a lot of emails regarding Shakti's positioning. As can be seen from our webpage, specific cores have been positioned to offer alternative to commercial cores including ARM's cores. Whether ARM gets affected by this or not is not for me to say. But to conclude that SHAKTI and the RISC-V eco-system in general could affect ARM significantly is not an unreasonable conclusion.So the reporter is well within the realm of reason to arrive at the conclusion he did. I am just making a distinction between causal reactions and intent !

On the contrary, we started Shakti because our lab can track technology faster than a commercial outfit ! I am an ex-industry architect and a startup CEO who came back to academia started this effort because the pvt sector was moving too slowly wrt CPU research and deployment. Done well govt entities can move really fast once you figure out how to deal with bureaucracy. And we can dream way bigger.

That means I have to develop all the code from scratch anyway. the arch lic just gets me a ISA spec doc.Might as well start with another ISA that is free. But the issue is bigger. Shakti is also an exercise in using a high level HDL. We would not exist but for Bluespec, we really get a 6x to 10x productivity increase over Verilog. I also get the ability to do true formal proving of the correctness of my code. There is a reason why DARPA hose bluespec for their secure processor work.

Also everyone is welcome to review our code and to contribute to the codebase. It is an open source project. IIT-M incubated it but we want it to be community driven. FPGA based dev packages should be announced by jan , based on standard low cost FPGA boards. Dev parts based on ASIC parts will probably be announced 2nd quarter of next year assuming Feb/March tapeout.We would be glad to help other universities do their own tapeouts. One of the goals of Shakti is also to demystify the backend process.

As the lead architect of Shakti and the guy who helped kick-start the project, I figure I am owed my 2 cents !

1. We never positioned it as an ARM killer ! That was the imagination of the reporter who wrote the article.

2. Shakti is not a state only project. Parts of Shakti are funded by the govt, these relate to cores and SoCs needed by the Govt. The defense and strategic sector procurement is huge, runs in the 10s of billions of USD.There is significant funding in terms of manpower, tools and free foundry shuttles provided by the private sector. In fact Shakti has more traction with the private sector than the govt sector in terms of immediate deployments.

3. The CPU eco-system including ARM's is a bit sclerotic. It is not the lic cost that is the problem, it is the inherent lack of flexibility in the model.

4. Shakti is not only a CPU. Other components include a new interconnect based on SRIO, GenZ with our extensions accompanied by open source silicon, a new NVMe+ based storage standard again based on open source SSD controller silicon (using Shakti cores of course), open source Rust based MK OS for supporting tagged ISAs for secure Shakti variants, fault tolerant variants for aerospace and ADAS applications, ML/AI accelerators based on our AI research (we are one of the top RL ML labs around). 4. the Shakti program will also deliver a whole host of IPs including the smaller trivial ones and also as needed bigger blocks like SRIO, PCIe and DDR4. All open source of course. 5. We are also doing our own 10G and 25G PHYs 6. A few startups will come out of this but that can wait till we have a good open source base. 7. The standard cores coming out of IIT will be production grade and not research chips.

And building a processor is still tough these days. Try building a 16 core, quad wide server monster with 4 DDR4 channels, 4x25G I/O ports, 2 ports for multi-socket support. All connected via a power optimized mesh fabric. Of course you have to develop the on-chip and off-chip cache coherency stuff too ! 8. And yes we are in talks with AMD for using the EPYC socket. But don't think they will bite.

Just ignore the India bit and look at what Shakti aims to achieve, then you will get a better picture. I have no idea how successful we will be and I frankly do not care. What we will achieve (and have to some extent already) is - create a critical mass of CPU architects in India - create a concept to fab eco-system ind India for designing any class of CPUs - add a good dose of practical CPU design knowhow into the engineering curriculum - become one of the top 5 CPU arch labs around

Shakti is already going into production. The first design is actually in the control system of an experimental civilian nuclear reactor. IIT is within the fallout zone so you can be sure we will get the design right. If you want any further info, mail me. My email is on the Shakti site. G S Madhusudan