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BrannonB

10 karma · joined June 22, 2018

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BrannonB··on Inside a Heist of American Chip Designs, as China Bids for Tech Power
Your second point was that HW engineers haven’t learned about sharing—as evidenced by the fact that they use a different term for it than SW does.

Again this is evaluating HW through a SW prism. Where’s github for bridge designers? rocket scientists? brain surgeons?

HW engineers share info in pretty much the same way that every other industry in the world does (except SW). The concepts are made available through patents, conferences, journals, and press releases. More detailed info is often made available through purchaseable IP.

Maybe it could be better, but there are good reasons that HW IP can’t be shared as easily as SW source code.

BrannonB··on Inside a Heist of American Chip Designs, as China Bids for Tech Power
25 years of high performance chip design.

Perhaps you’re an FPGA guy? The tradeoffs are different in that world.

BrannonB··on Inside a Heist of American Chip Designs, as China Bids for Tech Power
If you think Verilog is bad, you should see the languages used by heart surgeons, civil engineers and rocket scientists. The language of human biology is ridiculously verbose without even a hint of polymorphism. ;-)

My point is that it's a little silly to evaluate hardware engineering through the lense of software engineering.

In hardware engineering the part that looks like "software" (what a HW engineer may refer to as the behavioral RTL) is a small component of the total design effort. The tradeoffs are all completely different.

Computer hardware engineering is much closer to designing a bridge than it is to writing a software application. Debating the best hardware-descriptor language is similar to debating whether bridge designers should use No. 1 or No. 2 pencils.