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"self-driving safeguards fooled by $30 doll heads" https://electrek.co/2026/06/15/chinese-drivers-plastic-heads...

Yes, NOR Flash guarantees 20 years data retention. It's about $30/GiB.

All the big 3D NAND makers have already switched from floating gate to charge trapping. Basically the same as what you describe but basically the electrons get stuck in a non-conductive region instead of on an insulated gate.

It will. The big 3 (Micron, Samsung, SK Hynix) have announced they will quit making LPDDR4 so that they can make more (LP)DDR5.

Netherlands AND Holland? Isn't that the same place?

Also: Even while ASML steppers are built in Netherlands, there are a lot of other non-photolithography tools needed to build a fab in addition to the ASML tools.

Can you recommend a place to learn more about this? I have been curious about this topic but have struggled to find resources online describing the basic physics of electric flight propulsion.

I am pretty sure this sets a new record for highest Weissman score

I went to so many LAN parties at friends houses during high-school in the mid 2000s. Without this experience, I doubt I would have pursued electrical engineering and moved to silicon valley.

I think all the units so far are 3 motor (2 motors in rear) and therefore the rear differential lock is probably (planned to be) implemented by software that keeps the two motors in sync instead of with a physical mechanism.

Rivian "licensee" here. So far all updates have required you to press a button (in the car or on the app) to launch the update installer. Not sure how many weeks you can ignore it for as I never tried.

The extra 4 are for ECC

I have a new passively cooled N100 system I am planning to use as a router. I will try to run your tool on it when I get it running.

I agree. I never understood how this deal could have made business sense from the beginning. I grew up in south-east Wisconsin and I was disappointed at how gullible-seeming the local officials were. I was hoping I would be wrong and it would come to fruition some day, but unfortunately my initial gut feeling seems to have been right. I don't view Foxconn as a highly trustworthy partner, but I don't think the people in Wisconsin really understood who they were dealing with.

Infineon Aurix microcontrollers on TSMC 28nm have eFlash and RRAM available as NVM. https://www.infineon.com/cms/en/about-infineon/press/market-...

Power Via is more of a fab technology and AMD is fabless. Therefore not really possible to compare directly in this aspect. AMD relies on TSMC or Samsung to make their chips.

I had the same issue this morning on my RT-AC68U.

Arrow is the largest electronic component distributor in the world. They cater mainly to mid/large companies though, not hobbiests/etailing.

Also consider that most high density Flash today is made from TLC cells which have 8 distinct Vt levels each. That means in average case (i.e. random data) there is a minimum of 3.5 electrons per cell required.

In reality, much more than 1 electron is required to store a 0 or 1 with any level of reliability. On the order of 10s to 100s of electrons per bit even on leading processes.

Cypress Semi (now Infineon) FRAM is ferro-electric. FRAM is not affected by magnetic fields at all. MRAM is ferro-magnetic and is affected by magnetic fields.

I'm using a 5950X, and in the BIOS there is a setting where you can enter the power limit in Watts. So while the "X" CPUs consume more power as configured out-of-the-box, you can still set your own limit as desired.

Fed funds rate and total interest paid on outstanding treasury bonds are not a 1:1 relationship. The coupon payments of a bond are determined at the time of issuance. So for example if a 30 year bond was issued 10 years ago, the ongoing coupon payments that the US treasury is paying today on that bond are a fixed amount that was determined at the time the bond was issued 10 years ago. Every individual issuance of bonds has a specific coupon payment which is determined at time of issuance.

SRAM is ~10x higher cost per bit (due to memory cell size) than DRAM

Yes. But in layman's terms, wouldn't you just call that a "power plant"?

Fabs require 10's of MW continuous load. Not feasible to backup with diesel generator.

Disagree. Parent was discussing the need to reboot after a system has been on for a long number of hours. The failure mode, assuming it's related to the DRAM, would be an accumulation of bit-flips in the DRAM. Every memory has some FIT/Megabit rate. The on-die ECC added in DDR5 spec will be highly effective in addressing this failure mode.

Channel ECC is the ECC type most directly relevant for high clock rates and signal integrity aspects. I agree with you that Channel ECC becomes a practical requirement to meet the interface transaction rates of DDR5. It is also true that channel ECC is not mandatory in DDR5 and is not implemented by mainstream CPU platforms (like previous DDR generations).

All DDR5 DRAM ICs have on-die ECC. This is new for DDR5.

> moving from 200 mm to 300 mm requires a total redesign

That might be typically true, but it is not always true! The product line I work for produces the same IC simultaneously in both 200mm and 300mm fabs. Same mask set, identical device, no redesign. And we are moving more of our existing products into 300mm fab without redesign at all. Process is 65nm.

KeePass?