Comment by kken | Hacker News Reader

Comment by kken | Hacker News Reader

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>Now that the cost of wafers are going up, making a chip that is 50% better costs 50% more money.

This is not true. In the past, process optimization was straight forward: Make smaller transistors. The free ride ended with the 130 nm node more than ten years ago. Since then, manufacturers had to introduce new features to allow them to make transistors smaller. As you also noted, this leads to higher costs, and the economics did not scale proportional to Moores law anymore.

But: This has been going on for more than a decade. The technology did not fall off a cliff and it will not do so in the near future. Even if it is not possible to make transistors smaller, it is still possible to introduce new technological features to make them better and improve their area efficiency. There are still plenty of options, even without classical scaling aka Moores Law.

TL;DR: Nothing will go poof. We are going to see a less steep gradient, but this is part of a process that started ten years ago.

We'll see this year when the new process pricing comes out. The specific claim was not that the cost of the wafer is higher but that the $/transistor price is the same or worse for the new processes. If that holds true, then you're done with scaling by process shrinks. (Intel doesn't publish those costs of course but both Global Foundries and TSMC do)

   > But: This has been going on for more than a decade.
   > The technology did not fall off a cliff and it will
   > not do so in the near future.

If by this you mean that the $/transistor has been going down more slowly over the past decade, then I agree with that. The question is if that number will stop going down, and/or go up this year. That isn't a 'cliff' that is an inflection point, or perhaps a global minimum.

When that minimum is reached, the economics of the 'computer' business (scare quotes because I'm specifically referring to what is known as the PC laptop/desktop business) will change fairly dramatically.

>That isn't a 'cliff' that is an inflection point, or perhaps a global minimum.

No, there may be an inflection point in the metric "cost per standardized transistor". But this does not equal "cost per function".

There are manys way to utilize transistors more efficiently or still make them smaller while performing the same function. You have to realize that not all transistors in a chip are of minimum size due to circuit design requirements. Furthermore, only a fraction of the transistors are actually involved in performing the logic function you see from the outside. There is an increasing number of transistors spent on "housekeeping" functions such as clock distribution, power gating, bus drivers etc.

All of these can be improved by working on circuit design, improved layout software, optimzing the materials in the transistors etc. Of course this is less straightfoward than simply making the transistors smaller and therefore more expensive. Therefore we are going to see diminishing returns, but there will not be an inflexion point in the business model of the entire industriy.

Maybe we're talking about different things.

You wrote this: "No, there may be an inflection point in the metric "cost per standardized transistor". But this does not equal "cost per function"."

I claim that is does equal cost per function. Here is my reasoning on that, perhaps we can find out where we're disagreeing.

I'm going to claim that an engineering group E has a design D which they put on a process node Pn. That is a pretty easy claim since pretty much everyone who builds chips does that. :-)

I'm also going to claim that the engineering group is doing everything they can to efficiently use their transistors based on the evidence that efficiency is a key sales metric for chips today.

Then I'm going to claim that for a given design D, on a given process node Pn, you can compute an average cost per transistor for that pairing by considering the number of transistors in the design, the number of instances on a wafer, and the yield of good devices from that wafer, divided by the cost of that wafer.

Here is the assertion the article makes (and I agree with)

In the next process shrink, the cost of producing a wafer will be so high, there there will be zero change in the cost of chips produced on that process.

The engineering teams will do all they can, but the wafer costs will be so much higher that the cost per chip will either not change or go up. It will track signedness if not in magnitude this metric of 'cost per standardized transistor'. Once that is shown to be true, there will be no more investment in new processes because the economic value will not be there. And I claim that this will mean that from that point on chips will get more expensive over time with or without additional features being added.

I can't wait for the papers from the 2014 ISSCC which will tell me if I'm crazy or not :-)

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