No Moore? A golden rule of microchips appears to be coming to an end
economist.com
economist.com
Now that the cost of wafers are going up, making a chip that is 50% better costs 50% more money. That means that this years computer is more powerful than last years computer, except it costs 15% more (chipset cost is often 1/3 the cost of parts for a machine) And if your current laptop is 'good enough' in terms of power such that you aren't willing to pay 15% more. You don't buy it. And that is what is going to really be interesting here.
The new device costs more than the old device and isn't any more capable from a feature perspective.
30 years of PC marketing "lore" goes "Poof!" Now the only way to make your machine faster and cost less is to write more efficient software. Think about that carefully. It will define success in this next decade.
[1] In the chip business a wafer start is the process of sending 1 or more wafers through the process of being made into chips. It is the smallest unit of manufacturing.
This is not true. In the past, process optimization was straight forward: Make smaller transistors. The free ride ended with the 130 nm node more than ten years ago. Since then, manufacturers had to introduce new features to allow them to make transistors smaller. As you also noted, this leads to higher costs, and the economics did not scale proportional to Moores law anymore.
But: This has been going on for more than a decade. The technology did not fall off a cliff and it will not do so in the near future. Even if it is not possible to make transistors smaller, it is still possible to introduce new technological features to make them better and improve their area efficiency. There are still plenty of options, even without classical scaling aka Moores Law.
TL;DR: Nothing will go poof. We are going to see a less steep gradient, but this is part of a process that started ten years ago.
> But: This has been going on for more than a decade.
> The technology did not fall off a cliff and it will
> not do so in the near future.
When that minimum is reached, the economics of the 'computer' business (scare quotes because I'm specifically referring to what is known as the PC laptop/desktop business) will change fairly dramatically.
No, there may be an inflection point in the metric "cost per standardized transistor". But this does not equal "cost per function".
There are manys way to utilize transistors more efficiently or still make them smaller while performing the same function. You have to realize that not all transistors in a chip are of minimum size due to circuit design requirements. Furthermore, only a fraction of the transistors are actually involved in performing the logic function you see from the outside. There is an increasing number of transistors spent on "housekeeping" functions such as clock distribution, power gating, bus drivers etc.
All of these can be improved by working on circuit design, improved layout software, optimzing the materials in the transistors etc. Of course this is less straightfoward than simply making the transistors smaller and therefore more expensive. Therefore we are going to see diminishing returns, but there will not be an inflexion point in the business model of the entire industriy.
You wrote this: "No, there may be an inflection point in the metric "cost per standardized transistor". But this does not equal "cost per function"."
I claim that is does equal cost per function. Here is my reasoning on that, perhaps we can find out where we're disagreeing.
I'm going to claim that an engineering group E has a design D which they put on a process node Pn. That is a pretty easy claim since pretty much everyone who builds chips does that. :-)
I'm also going to claim that the engineering group is doing everything they can to efficiently use their transistors based on the evidence that efficiency is a key sales metric for chips today.
Then I'm going to claim that for a given design D, on a given process node Pn, you can compute an average cost per transistor for that pairing by considering the number of transistors in the design, the number of instances on a wafer, and the yield of good devices from that wafer, divided by the cost of that wafer.
Here is the assertion the article makes (and I agree with)
In the next process shrink, the cost of producing a wafer will be so high, there there will be zero change in the cost of chips produced on that process.
The engineering teams will do all they can, but the wafer costs will be so much higher that the cost per chip will either not change or go up. It will track signedness if not in magnitude this metric of 'cost per standardized transistor'. Once that is shown to be true, there will be no more investment in new processes because the economic value will not be there. And I claim that this will mean that from that point on chips will get more expensive over time with or without additional features being added.
I can't wait for the papers from the 2014 ISSCC which will tell me if I'm crazy or not :-)
Were still a long way away from that. Switching over to SSDs represents a huge speed boost, and given how young SSDs are, I suspect that there is still room for improvement in their speed. Also, there is likely improvements to be made in CPU architecture. We are still using x86, which has been improving incrementally with backwards compatible changes since the 70s. I'm not fammiliar with CPU architecture, but I suspect this means that there is room for significant improvements in terms of per transistor efficiency with the use of a novel CPU architecture. We could also see a drop in prices due to economical, not technological forces. For example, the price of a CPU is significantly higher than the cost to produce one. This is because you are paying for the development of the CPU. Without continuing fundamental improvements, we would expect to see the cost of CPUs fall to their marginal cost as development would no longer be necessary.
But then again, the gains possible may be more limited that you suggest because the transition from x86 to x86-64 did involve a number of major efficiency gains from changing register counts and how FP calculations where done. There may not be huge efficiency gains left that are easy.
With LLVM basically being a new runtime in some cases, we can do more complex compilation strategies such as was attempted with the Itanium architecture: https://en.wikipedia.org/wiki/Very_long_instruction_word
Who knows... I'm just brainstorming today. Happy New Years!
I seem to recall a comment a while back from an Intel chip designer guy saying that the x86 tax isn't as high as people think. Sure, the instruction set is super-crufty, but according to this guy they had found ways to implement most of the backwards compatible stuff in a way that's transistor efficient. He may have been biased, but didn't think the overhead compared to ARM was too significant.
I tried to google for the comment but couldn't find it, apologies for that. If someone with direct processor design experience would chime in that would be great.
But optimization is the root of all evil... or something.
http://www.brightsideofnews.com/Data/2011_5_6/Intel-Manufact...
Research and development efforts have been concentrated on !/W (bang per watt) for two reasons, the other one being cooling and power supply (battery consumption) on mobile devices in particular and the other reason is being able to run at higher clocks for longer before thermal throttling kicks in.
Power consumption and thermal output are relevant for all kinds of modern computers from smartphones to servers to supercomputers. Power consumption and thermal output are related in an almost linear proportionality, twice the power consumption, twice the thermal output.
Since clock frequencies stopped going up some ten years ago, we've had a 5x to 10x increase in single core performance (in addition to multi cores) thanks to increase in power and thermal efficiency and smaller transistors. Concentrating on power consumption keeps Moore's law alive rather than kills it.
But smaller size -> larger leakage current -> higher baseline power consumption.
For several years we have been at the point where the curves cross and power consumption is minimal. The strategy going forward is to turn off parts of the chip when they are not in use, or to reallocate functional units to other tasks (a la Hyperthreading).
The interesting issue has to do with Dennard's Law for power scaling, which said that power density would remain constant as we increased component density. This isn't true any more and that's part of the reason why multicore designs are the future (2 processors at 500MHz use less than one at 1GHz for a fully parallel workload).
In other words, it was the number of transistors that could economically be included in a single unit.
The Slow Winter by James Mickens https://www.usenix.org/system/files/1309_14-17_mickens.pdf
whatever architectures we come up with I think humanity will see increasing growth in computing power (perhaps not as insanely fast but fast) - but to use that effectively will no longer be a free ride for the developers
one last thing - More or Less podcast quoted this stat: a one billion FlOP/s chip today costs 19cents. In 1961 it did not exist but had we tried to build one machine to perform one billion operations a second it would have cost 1.1 trillion - or about the entire world GDP.
just puts Moore's law in perspective for me
That doesn't mean that after we reach this limit we won't be making quantum computers, or use other materials like graphene transistors that can probably reach TerraHertz clock speeds, which may even improve at a rate of 2x every 2 years, too. But it wouldn't be "Moore's Law".
We're also working on "brain-like" computers, but I think these and quantum computers will become "mainstream", in a general-purpose way (not just for very specific tasks), in a few decades, which should be quite a while after Moore's Law dies (in the 2020's).
So the most likely thing is that we'll use other kind of materials for the same type of "classical computers" for the next few decades, even after the end of Moore's Law, but they will improve through increasing their clock speed or through other ways, rather than getting that extra performance from adding more transistors.
A looser formulation talks about computing power. In that, we have been ahead of Moore's law with GPGPUs and vector units for quite some time. This formulation is more detached from physical process details and looks more like what the market can absorb.
In the end, what the market can absorb may prove the ultimate limit.
http://graphenewire.blogspot.com/2012/10/extending-memory-be...
http://www.techdesignforums.com/blog/2013/12/10/graphene-get...
(This is pretty different from what academia tells you...)
memristors
improved parallel processing
graphene
quantum
spintronics
optical
Did I miss any?
- II-VI channel materials on silicon
- Finfet, Nanowire FETS (the top down variant, not the academic bottom up version.)
- RRAM (Memristors are a sub-class of these devices. Memristors mainly exist in the PR department of HP)
- TSV integration
- 3D Flash
- Memory integrated processers (see Microns Automata)
As diversity decreases it will be much easier to write libraries that talk directly to the metal, protocols that write directly to the interfaces and applications that run completely isolated at native speed.
Without the towers of abstraction it is much easier to reason about the data structures of your input and output and design optimal algorithms. If we ever do come to this point there will be a renaissance in the field of computer science field.
EECS people make math convenient for themselves by pretending that voltage numbers and current numbers cancel out in certain ways. Otherwise they'd have to do really messy calculus. The problem is that this convenience is only true for circuits that are up to a certain speed. Past that speed, that way of calculating and engineering circuits starts to break down. We've hit those speed limits.
The field has chosen to react by instead switching to multi-core computers. The problem from a programmer perspective is that parallelism is difficult to write for. The reason it is difficult to write for is because of mutable variables, which are common in imperative languages. So that's driving the popularity of functional languages. However, not as many people are good at functional languages, since they tend to be more mature in academic circles, less mature for industry purposes, and generally more difficult to learn for people that are more used to procedural thinking than mathematical thinking.
So, if all those premises and implications are true that would mean that maybe if the EECS people stopped pretending that EECS circuits are simple and started doing the messy calculus, maybe we could start shrinking single-core chips again. But I'm sure I've messed up some of those premises. Anyone?
The slow-down in processor speed despite shrinking transistor is due to physical and design limitations. For one, it used to be that you could use more transistors to build more complex pipelines, branch predictors, etc. to allow you to turn up the clock frequency. But now we've reached the point of diminishing returns on this sort of optimization. Also, increasing the frequency increases the power, which causes problems for heat dissipation and chip lifetime. So we've cut back on frequency to lower the power consumption.