This is also very well documented. Probably as part of the assessment, but it's nice to see.

It doesn't appear to have any kind of interrupts, which is quite a limitation for actual usecases, but also makes the architecture much simpler.

The use of dual phase clocking is interesting. The document describes it as having the control and data paths operating on opposite phases. I'm curious as to where you got this technique from, since it's not common (apart from the use of both edges by DDR RAM). I also suspect that it would go away if you had better tooling for managing setup and hold violations (does logisim do that for you, or did you have to manage it manually somehow?). Not all FPGA tools like nonstandard clock architectures.