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Show HN: We built an 8-bit CPU as 2nd year EE students

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108 pointsCorRupT946 comments

Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs.

key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers

Hardwired control unit built entirely from AND/OR gate logic matrix

Dual-phase clocking to eliminate race conditions

Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional branching that saves upto 25% cycles when conditions aren't met

Full design specification document with version control

Since this was our first time doing such teamwork and a new thing we used RISC based system that fetches an 8-bit instruction from Instruction memory 4 bits of which translate to an instruction the last two bits are for source and destination registers. There are a total of 4 registers in the system with two memory units namely Data SRAM and I SRAM, the system follows a Harvard architecture.

There are design discrepancies too since it was our first time designing such a system and on top of that completely hardwired too.

To solve the problem of cold booting a bootloader is present too that copies the contents of a temporary ROM into instruction RAM and then hands over the reins to the CPU.

We also implemented conditional branching as well as early exit branching too that only checks for zero or carry flag and branches without wasting cycles, if the conditions are not met the Program counter increments.

Moreover we also created a complete documentation with version control describing each necessary part assuming prior knowledge.

Please take a look at it at https://github.com/c0rRupT9/STEPLA-1

For future development I want to implement a RISC CPU using FPGA's and connect it to an actual DRAM. We are also selling the full spec document and Logisim files for $5 to fund our passion https://tcfdiq.gumroad.com/l/zyyux Thankyou!

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"This makes the machine transparent in a way that microcode-based designs cannot be."

Every output bit m of microcode can be equivalently expressed as a logic function of n inputs where the microcode has n incoming address lines. This no less transparent than pure logic if you know the contents of the microcode. Microcode is often preferred because changing it is much easier than changing a bunch of gate logic. IMHO factoring your design into registers vs. control signals and putting the control signals into microcode makes the design more transparent than having a giant sea of gates.

Ben Eater's SAP came from "Digital Computer Electronics" by Albert Paul Malvino and Jerald A. Brown

https://en.wikipedia.org/wiki/Simple-As-Possible_computer

Yep this is how I built my SAP 20 years ago.

A 2nd year project back in the day was to build a 4 bit CPU on a breadboard. We had the advantage of having an ALU IC but was still quite tough to get working!

You were in good company. The Xerox Alto CPU used four 74181 ALUs.

So this was all just simulated? Where are the pictures of the build?

Back in the day i built a 4-bit CPU on a breadboard (it was huge actually spanned 3 breadboards). Programming the ROM by hand like cavemen (to be fair it was the cave ages). We didn’t carry cameras in our pockets so sadly we didn’t get a picture.

My "back in the day" project, which everyone in class (could work in team up to 3) had to do was a wirewrapped breadboarded 8-bit CPU. We had to demonstrate it solving some problem. Extra points for doing something with an I/O channel.

At the end, my team drew straws to see who would get to keep it. Alas, I didn't win.

CMU in 1986.

I did the same (4-bit cpu, 11 instructions) in my Microprocessors class, out of 74-series logic, one GAL20V8 to handle the SLE instruction and an EPROM (not an EEPROM - one with the clear window you exposed to UV light to erase.

That was also where I learned about ground-bounce & dynamic IR-drop effects due to those long looping wires between breadboards.

That was a fun class.

Raise your hand if you still have a UV eraser at the bottom of a cabinet somewhere.

I always used the one in the school lab. Since that’s also the only place where I could program the eeprom :)

We actually made it on breadboards, since it was hardwired the bread-borad is now a sea of wires everywhere, and some things are not working too. I am thinking of getting a custom PCB just for the control unit to make it presentable.

This is also very well documented. Probably as part of the assessment, but it's nice to see.

It doesn't appear to have any kind of interrupts, which is quite a limitation for actual usecases, but also makes the architecture much simpler.

The use of dual phase clocking is interesting. The document describes it as having the control and data paths operating on opposite phases. I'm curious as to where you got this technique from, since it's not common (apart from the use of both edges by DDR RAM). I also suspect that it would go away if you had better tooling for managing setup and hold violations (does logisim do that for you, or did you have to manage it manually somehow?). Not all FPGA tools like nonstandard clock architectures.

Actually this was my very first implementation, even in simulation it had to be made on boards someday keeping timing skew and capacitance of boards in mind i decided to flip the clock, this will give the control unit a head start of half a cycle and get everything ready before the clock reached the next high, this trick was also used in one of the projects I mentioned at last page in the document. I had to probe and check every signal keeping the standard gate delays of 74 series in equation too!

Not having interrupts isn't necessarily a problem. In fact if you want to be sure that the processor behaves deterministically then you might choose to not have interrupts. I remember seeing an article about the British RAF commissioning a CPU design and explicitly forbidding interrupts for that reason. Unfortunately I don't remember where I saw it so I can't check to see if my memory is faulty.

The dual phase clocking is perhaps inspired by the 6502.

Awesome project, re fpga implementation one option you might want to explore are used Bitcoin miner control boards if you want the best logic units/$ ratio. I've used the EBAZ4205 (zynq 7010) control boards with a cheap/generic FT2232HL dev board and it works great. Of course it's a bit more of a pain compared to a regular dev board

If they are taking digital design classes, they'll probably be given something like a DE0-Nano that can run this just fine.

If I tell what we got for our projects you would be disappointed at my university. We get nothing not even a single FPGA kit is available in the whole department.

This is a nice idea! I never knew of this will look into it. Actually our university did not even provide us with chips to make breadboard version we had to source everything ourselves.

I did something similar for a school capstone project. It brings back memories. Writing Verilog, working with FPGAs, that sort of thing. But this goes even further and actually gets into hardwired implementation, which is really impressive. Actually, using if else statements just creates MUXes, so you don't have fanout issues to worry about. But for something like this, you would have to handle timing calculations for rising and falling edges. It is really remarkable.

Very nice. I wonder if implementing a one-instruction set computer (for example something that implements Adrian Cable's subleq VM, see https://www.ioccc.org/2025/cable/) would be educational and whether it can make the design of a computer from discrete logic chips simpler or more complex. Though it would very likely not be as efficient.

The simplest processors use one clock per instruction with a Harvard architecture. This allows their control unit to be a combinational circuit instead of a Finite State Machine (and depending on how your memories work you might even avoid having an instruction register).

Most one-instruction processors take multiple clocks and often need extra registers (for fetching 16 bit addresses from an 8 bit wide memory, for example) [1].

The four instruction MCPU [2] is not as bad to program as the one-instruction computers (it still needs 10 times as many instructions as a RISC-V, for example) while being very simple. Making it Harvard allows it to be slightly simpler and making it 16 bits allows it to run non trivial programs [3].

[1] https://github.com/jeceljr/SBN/blob/master/sbn.pdf

[2] https://github.com/cpldcpu/MCPU

[3] https://github.com/jeceljr/digitalCPUzoo/tree/main/MCPU

the rom-to-ram bootstrap is a nice touch. after it hands over, what stops the bootloader from writing to I-SRAM again? a mode flag in the control matrix?

Actually it writes again after every hard reset. but i added a push button to stop it, logically speaking we only turn our computer on once and then run it till our tasks are done. Similarly we do it here, but still the best option for me was to use a separate ROM address in Program counter and use it. It was a simple use case where you Just copy everything the the RAM from permanent memory.

Computer architecture (I think my uni named it comp org) was one of my toughest courses in undergrad! It steered me away from hardware. I now wonder if that is still the case today? ARM has exploded onto he scene and I'm fascinated by the sheer amount of development going on in the chip space.

Many principles in computer architecture were discovered loooong ago. Pipelining, multi-core cpu's, virtual memory, various types of caching, etc etc. It's just that today's tech squeezes orders of magnitude more logic into a mm^2. So the scale of what's considered a small or big project has changed.

Obviously that requires a more rigorous approach. So I'd expect courses in this field to put more emphasis on testing & validation methods (and tools to do that).

> ARM has exploded onto he scene

ARM is mature tech now. I'd say most excitement is around RISC-V these days. Well that and GPUs, AI accelerators, FPGAs, manycore cpus, photonics, quantum computing, ...

I hd to do a 4-bit version of this back in 2006 for my Computer Science undergrad. Interesting to see EE students doing it as well. Like many people here, we had to build it on actual breadboards. Which I think adds a ton to the experience.

Are you from Pakistan? I have an Alchitry Cu FPGA board for my personal use if you want to borrow it for implementation. Awesome project btw!

Sure! will mail you.

Nice developments, keep going

Logisim was the shit back in Uni

Very implressive tbh

You should include a screenshot of the logisim diagram

Added it to readme on GitHub at the start!

amazing 2nd year i was playing starcraft all day

You'd learn a similar amount doing this project with AI

That ipc lol were all 8bit CPUs less than1 instruction per cycle?

With all the talk about developers being lazy and younger folk not understanding the technology they use, it is always great to see examples of core foundational work still being done. Makes the rest of that talk feel like fear mongering.

I did an undergraduate electrical engineering degree some years ago. Building a CPU much like this one was the final project in our second digital design class. The difference here from the usual approach, as they point out, is that this is a gate-by-gate design you could assemble out of 74-series logic gates on a breadboard rather than the more common Verilog/VHDL designs that target FPGAs. Definitely a more tedious, time consuming approach, but I'm not convinced it's more conceptually difficult. By the time you're building a CPU, you've probably already built the component parts like the adders out of pure logic gates, anyway.

Not to say that this is easy, but I think you'd find that a whole lot more people are doing this kind of thing than you might think.

Every generation in history has said the younger generation is lazy. Didn't make it true when I was a young xenial / millennial and I suspect it's not true for Gen Z and Gen Alpha either.

Actually I am lazy but I love to do what I do and see it through!

Neat!

Now do it the other way round and make the 8 bit cpus become a 2nd year EE student.

>>me and my friends ...

My friends and I...

If you're going to be a pointless language pedant, it really helps if you don't fuck it up.

OP said:

> me and my friends together built an 8 bit CPU…

– and if one replaces that with your suggestion:

> My friends and I together built an 8 bit CPU…

– you'll find that you are, gleefully, wrong.

For those unaware, the simplest test for 'me and x' vs. 'x and I' is that, in the latter case, you should be able to remove 'x and', and have the sentence still make sense.

For example, 'Me and Lucy went to the shops' is technically incorrect, because 'Lucy and I went to the shops' makes sense if we remove Lucy. 'I went to the shops'.

The pendant's adjustment fails this test:

> I together built an 8 bit CPU

I downvoted the original comment because grammar pedantry adds nothing here. But if you're going to correct a pedant, you've got to be right. You're applying a test you don't understand and you messed it up.

"I" is the subject of the sentence, or the person who is doing the thing. "Me" is the object of the sentence, or the thing that is receiving the action. Since he and his friends are the ones who did the building, "I" is the correct pronoun.

Going back to the test you gave, the correct way to apply it is to replace entire the noun phrase with "I" or "me". The noun phrase here was "me and my friends together". "I built an 8 bit CPU" vs "Me built an 8 bit CPU". The former is the obviously correct one.

Obviously one needs a lesson in English sentence construction. I had those lessons beginning in grade school and ended in college. I'm not sure you've had anything beyond the internet.

> pendant

See https://en.wikipedia.org/wiki/Muphry%27s_law

Me together built... doesn't make sense either

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