Yes the FPGA does digital beamforming and there will be published FPGA pin constraint files so you can write your own Verilog.

For IQ samples, you can stream a continuous 60 MSPS IQ beam over the Ethernet, but for custom beamforming algorithms, the processing needs to be distributed across the FPGAs (for MoonRF it is a SERDES daisy chain, using the same FFC connectors as the links to the RPi-5).

Yes I'll put some newer block diagrams on the website this week. Thanks for the reminder.