Is there really a point to making gates even smaller when the leakage is already so atrocious? The future of Moore's law is in whoever finds a way to make a modern PC that doesn't pull a god damn kilowatt.
But to address leakage there are already the gate-all-around transistors [1], which are in semiconductor companies roadmaps [2].
[1] https://www.asml.com/en/news/stories/2022/what-is-a-gate-all...
[2] https://www.anandtech.com/show/16823/intel-accelerated-offen...
Noctua and gamers nexus have shown just how competitive the air cooler market is for cooler performance....and how the CPU package deforms over time impacts cooling.
Personally, I think we could make CPUs that are much bigger and stack the transistors and chips even higher if we managed to get the cooling figured out.
Imagine a 3d tower of a CPU where cooling channels exist in between layers
# = your silicon chip @ = a cooling channel
Now imagine stacking like the following
###### @@@@@ ###### @@@@@ ###### @@@@@ ######
This could be a starting point for stacking chips.....sort of like how 3d nand is stacked....yet instead we stack the CPU wafers and have cooling channels in between them. You could even make the CPU and cooler, and have the chip interconnect going up the sides.....