Is the Future of Moore's Law in a Particle Accelerator? | Hacker News Reader

Is the Future of Moore's Law in a Particle Accelerator?

spectrum.ieee.org

42 pointselashri27 comments

Laser wakefield accelerators should help with miniaturization of the particle accelerators needed for free electron lasers. It seems like to get the beam energy levels required for a FEL we need methods for staging wakefield accelerators. Staging has been demonstrated but perhaps not scaled up in beam energy? It’s been a few years since I’ve checked in on this domain…

It is already possible to reach 800 MeV (the energy for an EUV FEL according to the article) with single-stage laser wakefield accelerators. The problem is doing so with sufficient beam quality, reproducibility and repetition rate. The energy efficiency would also be a problem, as it is nowhere close to what an energy recovery linac could achieve.

I'm not an expert in this domain and I really wish I could understand more of the issues on efficiency--it still seems like there are major engineering gaps preventing a table-top FEL from existing. I know a little about beam quality issues, but don't really have any sense for the power scales and efficiencies. Are we talking like 10x more power for the same EUV beam from Laser plasma accelerators over an energy recovery linac or an ASML unit?

If the repetition rate is too low, is it possible to re-use an electron beam and use mutliple undulators for multiple EUV beams with separate lithographic reticles? Is it the chirped-pulse-amplified lasers that have slow rep rate or is it possible to have a single driving laser with multiple plasma targets?

Is there a way it becomes viable if you can make something that is dramatically lower in cost even if it burns 10x the power?

The issue with the efficiency begins already with the high-power lasers that are needed for wakefield acceleration, which have a typical wall-plug efficiency of ~0.1%. From that, only about ~1% of the laser pulse energy gets transferred into the accelerated electron beam. And only about ~0.1% of that gets converted into light again during the FEL process.

All together, that would mean an efficiency of ~10^{-8}, which is about a million times smaller than for the ERL (I'm no expert there, but I think in the article they mention 1-10% efficiency).

There are prospects for much more efficient high-power lasers, but there's still a long way to go.

I don't know what would dominate the costs in this particular case, but given the low efficiency and reliability (high-power lasers break often) as well as the other issues, I wouldn't bet on wakefield accelerators as an alternative.

Thanks for your notes! I've only worked with solid state lasers that are pretty efficient and would have figured 10% aught to be possible for a CPA from wallplug to multi-terrawatt beam. I'm not sure how losses would go in the chirp pulse amplifier, plasma or FEL stages though.

I think we could afford a 10^-6 wall power to EUV beam loss and still be economical probably not 10^-8... my rough estimate is that for your 100W EUV beam equivalent to what ASML provides you can afford to burn on the order of 100MW for four years and still use less dollars to pay for that power than the capital expenditure for your ASML EUV system.

Extremely small wavelengths can be achieved using beams of electrons in place of beams of photons, as in Scanning Tunneling Microscopes and electron diffraction.

Do you know if there is any thought of developing “electron beam lithography”, where an electron beam would etch the pattern on silicon and not merely be used as a source of secondary photons?

As I understand it electron beam lithography exists as a technology (and is maybe used for reticles? not sure) but the throughput is way too low for production. Its several orders of magnitude slower than euv apparently.

Interesting. With all the mega bucks and efforts to produce smaller wavelength photon beams, I wonder if a comparable investment would increase throughput? Or maybe there is an insurmountable technical hurdle.

The problem is pretty fundamental. Optical approaches illuminate the whole chip at once. Electron beams have to go transistor by transistor.

Why? What prevents you from illuminating the whole chip with electrons? Can't get an electron source "bright" enough? Uniform enough? The chip can't handle that much current? Or what?

The problem is that you can't make mirrors or lenses for electrons, so the mask can't be bigger than the chip. There's also the significant problem that shooting electrons at things tends to damage them, so making a mask that can survive the process sounds very tricky.

Slower because steering a beam around to draw a pattern is much slower than using a light source through a mask to expose the entire pattern at once.

I think electron beams might be used to make some of the masks for regular lithography, but I'm sure there is someone here on HN with actual experience in these areas with actual knowledge ;-)

Yeah I’m just a casual Asianometry viewer and we’ve already reached the limits of my knowledge on this topic.

Atomic semi might be pursuing that: https://news.ycombinator.com/item?id=34907885

Interesting — thanks

Ebeam-litho is how wafer masks are made for photo-litho. It’s very precise but very very slow…

For background, there’s a great write up of current approaches at https://spectrum.ieee.org/high-na-euv

No mention of the SSMB project? AFAIK that one is further along than the EUV-FEL approach

Is there really a point to making gates even smaller when the leakage is already so atrocious? The future of Moore's law is in whoever finds a way to make a modern PC that doesn't pull a god damn kilowatt.

Those are two different problems. And this is just research for now.

But to address leakage there are already the gate-all-around transistors [1], which are in semiconductor companies roadmaps [2].

[1] https://www.asml.com/en/news/stories/2022/what-is-a-gate-all...

[2] https://www.anandtech.com/show/16823/intel-accelerated-offen...

Also backside power delivery supposedly helps a lot by letting you use bigger (so lower resistance) wires.

As long as overall power consumption keeps decreasing, yes.

I disagree. The future of Moore's law is whoever finds a way to cool a kilowatt cpu effectively.

I agree with you in a lot of aspects. Obviously extreme hyper NA EUV is possible....and with Wakefield accelerators we might be able to shrink the size of these machines to a more feasible size. And the gate all around transistor seems like its how the industry plans on handling leakiness when shrinking the size of our circuits.....yet cooling is the largest issue we face in some ways.

Noctua and gamers nexus have shown just how competitive the air cooler market is for cooler performance....and how the CPU package deforms over time impacts cooling.

Personally, I think we could make CPUs that are much bigger and stack the transistors and chips even higher if we managed to get the cooling figured out.

Imagine a 3d tower of a CPU where cooling channels exist in between layers

# = your silicon chip @ = a cooling channel

Now imagine stacking like the following

###### @@@@@ ###### @@@@@ ###### @@@@@ ######

This could be a starting point for stacking chips.....sort of like how 3d nand is stacked....yet instead we stack the CPU wafers and have cooling channels in between them. You could even make the CPU and cooler, and have the chip interconnect going up the sides.....

Moore’s law per power died a while ago, cost per transistor before that, but the speed advantage of waiting 10 or 100 times less is still attractive.

This is Dennard's scaling.

Is that down to leakage or the sheer amount of transistors / work being done?

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