You had me in the first half. You're absolutely right about the shortcomings of Verilog. I see a lot of similarities between it and PHP - where the language has developed features it doesn't really understand and therefore hasn't quite got right. But it has developed. It goes a fair way to let you do things that otherwise you have to generate code for. And everyone rolls their own code gen. VHDL is vastly inferior at this point in terms of its capabilities especiallly in the verification space, and where Verilog loses in terms of Loose typing it can ameliorated with linting.