Comment by gsmecher | Hacker News Reader

Comment by gsmecher | Hacker News Reader

From 2020. This article is hagiography - while it's worth celebrating how far HDL has come, it's also worth looking into what's holding us back. Verilog is one of those things, so here's a short complaint.

Modern Verilog/SystemVerilog is profoundly hobbled by Verilog's origins as a loosely typed, ad-hoc language (think: Perl, MATLAB, or on an especially rough day, PHP). It has evolved in a committee-and-footgun-rich way reminiscent of C++ - to the point that the article ends by admitting "[i]t is difficult if not impossible for any one engineer to be fluent in the complete language." The language is simultaneously too simple and too complex.

I write VHDL where I can, am hopeful about Clash/Chisel/Lambda, and am optimistic that efforts like CIRCT can replace Verilog in its weird role as machine-produced and machine-digested RTL. In the meantime, though, I don't think Verilog's supremacy is something to be celebrated uncritically.

You had me in the first half. You're absolutely right about the shortcomings of Verilog. I see a lot of similarities between it and PHP - where the language has developed features it doesn't really understand and therefore hasn't quite got right. But it has developed. It goes a fair way to let you do things that otherwise you have to generate code for. And everyone rolls their own code gen. VHDL is vastly inferior at this point in terms of its capabilities especiallly in the verification space, and where Verilog loses in terms of Loose typing it can ameliorated with linting.

The "language wars" narrative feels pretty played-out, so I'm not going to get drawn into it. In the software world everyone seems to recognize that different languages have different strengths, and that there's room for more than one. I'd love to play to the strengths of each language (example: SystemVerilog for verification; VHDL for fixed-point DSP).

A polyglot HDL world is elusive because simulator vendors insist on charging incrementally for language support, and open-source tools fall into either camp Verilog or camp VHDL. This is just another thing to lament.

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