I guess the interesting question is how this approach compares to FPGAs in terms of cost and performance. Given the functionality of the different chiplets as soft IP, wiring them together and loading the design into an FPGA should be easy enough. So how much more would I have to spend on FPGAs to implement the same functionality as a typical combination of chiplets? How much more to match the performance? Or are there no FPGAs that could fit the functionality or match the performance?