Do you have any further information on how/if there are "practical" ways to get custom maskless VLSI there?
Due to the practical limitations on "direct" reticle size for maskless lithography, you already need reticle stitching for matching any modern (think, this century) mask-based photolithography VLSI capabilities, and thankfully most maskless reticle stitching tactics can be scaled to an entire wafer. [0]
Some tactics likely need mechanical re-positioning of the write head to different parts of the wafer due to Etendue limitations of commercially practical optics (keeping sharp focus across the entire optically reachable area, within which they rapidly write individual reticles at reticles-per-second rates IIUC usually somewhere in the audible range), but the same mechanism that's used to track alignment of the lithography layer to those of previous steps, can typically be adapted to work across mechanical scanning within exposure of the same lithography layer.
While wafer-scale integration naturally needs defect-compensation, modern micro-channel liquid/phase-change cooling can already handle heat removal at desktop Zen3 chiplet power densities without needing a heat spreader to thin the power density out.
Tactics like feeding in the liquid parallel to the chip, and letting it boil on the chip-side of the structure, to then let the vapor escape normal to the chip (if it's flat, this would be vertically upwards), can scale to very large areas because you can put occasional liquid feed pipes in the vapor-space that are thick enough to not cause excessive pressure loss, and thus scale from having to pass the liquid sideways across the entire chip to something with less flow resistance (pressure drop) for the escaping vapor.
3D printing can manufacture those intricate structures that allow exceeding areal power density limits of nucleate boiling (which are around 10~30 W/cm² for chemically/environmentally tame hydrocarbons (e.g. Pentane, boiling comfortably at 1bar/2bar/5bar at, respectively, 36°C/58°C/92°C, low toxicity but more flammable than gasoline), and around 100 W/cm² for water (sadly, 120°C surface temperature isn't practical for silicon CPUs)).
Wafer-scale processors are just extremely capable compared to normal reticle-limited ones, see e.g. how Cerebras manages to run fluid dynamics simulations for things like iirc helicopters at/above realtime speeds, enabling predictive control in aerodynamically unstable situations.
Allowing manufacture of processors not limited to special reticle-border-crossing wires is, IMO, quite ground-breaking. Imagine things like hex or triangle grid mesh networks on the chip, and just overall a far more homogenous mesh topology just about flexible enough to route around the defects, possibly using just the normal required back-pressure routing to deal with the congestion-hotspot from needing to divert around a disabled cell (and do so without the greater surroundings needing to even be aware of that cell being disabled). [At worst a disabled area would need to be turned into a rectangle to make adaptive Manhattan routing work. The software would need to be taught to deal with holes in the physical-location-based address space, but many algorithms are inherently tolerant enough to deliver proper useful results even with their data grid having holes/crystal defects, and a physically homogenous grid of cores (should, IMO) fit(s) those better than one less-homogenous that can fully mask deactivated cores (like Cerebras's device).]
And beyond wafer-scale processors, analog VLSI processors (they could be manufactured using traditional photolithography) are awesome.
There are just two major obstacles in the way of utilizing them:
1) they don't allow much flexibility in even simple operating parameter tuning (let alone larger FPGA-like reconfiguration) to use a generic chip in many situations/different devices. Thus they need a low practical MOQ for broad utilization.
2) due to difficulty with simulating/modeling the entire dynamic system they operate/control, substantial iterative experimental tuning of the hard-coded (though literally the shapes of the devices manufactured in the integrated circuit) parameters will be necessary during product development. Mask-less lithography is inherently able to manufacture down to single-digit MOQs (only really limited by stochastic yield/binning and multi-step-process lead times).
[It's trivial to sample the hard-coded tuning parameter space, via simulating behavior differences, and then sampling finely enough to not miss the perfect range of parameter values as a result of manufacturing yield/rejects poking holes into the sampling grid.]
I believe there are substantial opportunities in electronic power converters, due to the frequencies unlocked by recent advances in [high-frequency-capable] SiC and GaN power transistors.
And how multi-MHz switching shrinks the size of capacitors/inductors/transformers, in exchange for demanding extremely rapid control (and worse, often limiting the current of a single module due to speed-of-light effects, which implies many individual controller chips).
For reference, here's a list of commonly-encountered electronic power converters that typically aren't made in the quantities needed to make traditional analog/mixed ASICs economically feasible:
"computer power supply",
"high-efficiency electronic motor controller" (which are just fancy variable power supplies commanded by a controller that translates input commands and possibly sensor feedback into drive voltages),
"solar panel to power grid adapter" (regardless of whether the grid is a normal AC grid needing it to be an inverter, or if it's a DC grid needing it to only adapt the voltage),
"battery charger" (essentially all types, except if the voltage matching is done by an external device like how electric cars with DC fast charging only request the desired voltage from the stationary "charger" (itself "just" a variable power supply)),
etc.
[0]:
[With DLP chips, you get single-exposure pixel counts on the same scale as contemporary TFT (I e., active, large-panel) LCDs (the kind used in flat screen computer monitors and TVs; this stems from a large (if not the largest) market for DLP technology being projectors/beamers), and electron-beam approaches run into issues with deflection mechanism linearity (i.e., pixel spacing uniformity between center and borders) in the 1000~100000 (1k~100k) linear pixels (width, in the fast axis).]