Not quite. We basically don't care about 3D density at the moment. The plane of the wafer is ultimately what matters from a density perspective. Right now we're actively cutting into 3D density heavily for small 2D density gains.
I assume you care about 2D vs 3D for different variables, no? I agree 3D, at least while H<<W, doesn't matter for clock speeds, but wouldn't it still play a significant role in the power characteristics, particularly things like gate capacitance? Genuinely curious. Going off of my memory of my Physics of CompE class ~10 years ago at this point.
If the gates of the transistor are taking up all that space, but FinFETs and newer gate all around FETs have significantly sized voids in 3D space, you just can't practically use those voids for anything else without cutting into yields or having awful leakage issues.