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Comment by conjecTech | Hacker News Reader

Transistors at that scale are 3D rather than 2D, so the expected scaling ratios no longer apply. If you wanted double the density of a 2D transistor with 5nm features, you'd need to scale down to 3.5nm, but if you wanted to double the volumetric density in 3D, you'd only need to go down to 4nm.

How do you make meaningful compare to past generations with that being the case? You could then just describe it in 2D terms, and refer to your 4nm process as 3nm. Then all of the same rules of thumb still hold.

I assume this is responsible for at least some portion of the deviation and confusion, though maybe not all of it. Happy to be corrected if I'm wrong.

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The industry roadmap has adopted a new nomenclature to try to clear this up, but it remains to be seen if the major companies will adopt it.

In any case, people who jump to saying these process node names are bullshit because they don't simply map to something like a wire width are kinda naively missing the point. Everyone in the industry understands what's going on and these fab node names emerged naturally as a shorthand way of describing changes to design rules that are a lot more complex and varied. That's still true today.

Media however, is not the industry, and the media has done a poor job of reporting based on industry names, rather than general public friendly names

Also, in practice, no one cares how "tall" the chip is — 100nm vs 200nm is ... unimportant. The result is that the volume of the poly hasn't changed much in the last ~10 years. Transistors are still biggish; just with tiny footprints. (And really, it's pitch density: we can pack the poly tighter.)

Not quite. We basically don't care about 3D density at the moment. The plane of the wafer is ultimately what matters from a density perspective. Right now we're actively cutting into 3D density heavily for small 2D density gains.

I assume you care about 2D vs 3D for different variables, no? I agree 3D, at least while H<<W, doesn't matter for clock speeds, but wouldn't it still play a significant role in the power characteristics, particularly things like gate capacitance? Genuinely curious. Going off of my memory of my Physics of CompE class ~10 years ago at this point.

If the gates of the transistor are taking up all that space, but FinFETs and newer gate all around FETs have significantly sized voids in 3D space, you just can't practically use those voids for anything else without cutting into yields or having awful leakage issues.

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