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Comment by MayeulC | Hacker News Reader

You can get pretty far with yosys, icarus verilog, various spice simulators and gtkwave, but I agree.

At least, interchange formats are pretty well specified (netlists, HDL, waveforms...), maybe except for the proprietary "Open Access" format.

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If you suggest using those tools for most industry semiconductor work you’ll be laughed out of the room. I wish it wasn’t the case, but these tools aren’t good enough for most industry use cases.

I know almost nothing about this area. Just how much effort do you think it would take to get these tools to "good enough but no more"/MVP? Days/Weeks/Months/Years/Decades etc.?

From what I have seen of both the open source and commercial EDA software, I think it would take a well funded team somewhere around 4 years of development to catch up with the current state of the art. If we're talking about EDA emulation hardware, probably more like 6 years, since these usually have custom Basics designed for them.

Maybe you could cut a year off of those and still have something that is good enough but not state of the art.

Aside from what was already mentioned in another comment, one of the largest things lacking in this area is not having dedicated support. These tools are maintained by only a few individuals, and if you need a feature of bug fix, you either need to implement it yourself or wait a long time for a fix.

If you need a feature or bug fix from Cadence, Synopsys, or Mentor, I've usually had releases that fix the issue within a week or two.

The article seems to imply that EDA vendors contributing to a common open source project is where EDA ought to go moving forward. That's a step in the right direction because it'd fix this support issue I mention. But it probably won't fix the cost issue.

The problem (or perceived, I guess) with yosys is that it is not production safe. It does still, from time to time, produce catastrophic synthesis errors. If you're going for tapeout, a synthesis issue due can cost millions in wasted parts, and so most in industry are willing to pay the astronomical costs of whatever synthesis tools of choice because they are significantly less than the cost of an error. For FPGA stuff though? Yeah, yosys all the way--I'm willing to forgive the worse optimization for it being FOSS :)

I know industry gets away with it, but I think a post synthesis simulation run is in order until the tools can prove that their output is correct.

I understand your point, though I have never done synthesis at that scale.

Still, with yosys, Verilator and other tools, you can have some form of CI. Using multiple simulators can reduce the number of bugs, and no one in their right mind would spend >100K for a tapeout without checking it with all available tools.

I can see day-to-day development being performed with yosys and others, with punctual verification (including the final one) on other simulators.

There's plenty of advantages: local/offline development environment, CI, multiple tools to help home in on issues, better perf in some cases, no fighting over license seats (heck, even one seat should be enough).

Now, if companies would donate a few percent of their license costs to FLOSS alternatives, the software landscape would be very different indeed.

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