Hacker News Reader

Comment by vmception | Hacker News Reader

what use case does this level of bandwidth open up, and I am not able to understand why the article thinks SSDs are one of them. PCIe already provides more than enough bandwidth for the fastest SSDs, am I missing some forward-looking advancement?

View on HN

CXL puts PCIe in competition with the DDR bus. The bandwidth was already there (now doubly so), but CXL brings the latency. That's exciting because the DDR bus is tightly linked to a particular memory technology and its assumptions -- assumptions which have been showing a lot of stress for a long time. The latency profile of DRAM is really quite egregious, it drives a lot of CPU architecture decisions, and the DDR bus all but ensures this tight coupling. CXL opens it up for attack.

Expect a wave of wacky contenders: SRAM memory banks with ultra low worst-case latency compared to DRAM, low-reliability DRAM (not a good marketing name, I know) where you live with 10 nines of reliability instead of 20 or 30 and in exchange can run it a lot faster or cooler, instant-persistent memory that blurs the line between memory and storage, and so on.

> CXL

Thank, that it quite an interesting technology I wasn't aware of. Apparently Samsung already made a CXL RAM module for servers in 2021 (1). I wonder how Intel optane would have been if it had used CXL (assuming it didn't).

Side note but AMD devices' (laptops/NUCs) lack of thunderbolt or pcie access is why I'm quite hesitant to buy a portable AMD device which is quite unfortunate. I really hope AMD/their partners can offer a solution soon now that thunderbolt is an open standard.

1. https://hothardware.com/news/samsung-cxl-module-dram-memory-...

Plenty of people are betting that future Optane will use CXL; it makes perfect sense. Sapphire Rapids doesn't support CXL.mem so we may have to wait for 4th gen Optane on Granite Rapids.

Current SSDs, but there is literally nothing stopping people from putting PCIe switches in place and maxing out literally any PCIe link you can create.

The limit then becomes the amount of RAM (or LLC cache if you can keep it there) bandwidth in the machine unless one is doing PCIe PtP. There are plenty of applications where a large part of the work is simply moving data between a storage device and a network card.

But, returning to PtP, PCIe has been used for accelerator fabric for a few years now, so a pile of GPGPU's all talking to each other can also swamp any bandwidth limits put in place between them for certain applications.

Put the three together and you can see what is driving ever higher PCIe bandwidth requirements after PCIe was stuck at 3.0 for ~10 years.

PCIe 4.0 x4 lane provides enough bandwidth. Ish... we've already capped out with 8GBps SSD actually. PCIe 4.0 x4 lane is now the limiting factor.

PCIe 6.0 1x lane would provide the same bandwidth, meaning you run 1/4th as many wires and still get the same speed.

Alternatively, PCIe 6.0 4x lane will be 4x faster than 4.0, meaning our SSDs can speed up once more.

From what I understand, internally an SSD's bandwidth can be easily scaled by spreading reads and writes across arbitrarily large numbers of NVRAM chips within the SSD.

So, you can just create SSDs that saturate whatever bus you connect them to.

In a sense then, it is the bus specification itself that limits SSD throughput.

You can make SSDs arbitrarily fast by just making them wider/more parallel. The reason it seems like PCIe 4 or 5 is "fast enough" is because the SSDs are co-designed to suit the host bus. If you have a faster host bus, someone will market a faster SSD.

> PCIe already provides more than enough bandwidth for the fastest SSDs

Today, yes and a few tomorrows as well. But even when a standard is announced as finalized, it can be a long time (Years even) until it makes it's way onto motherboard of the consumer space. By which time, the current goalposts may start looking closer than expected.

I'm just glad they have one number, no endless revisions and renaming of past releases and with that - thank you PCI-Sig.

current top of the line SSDs are close to maxing out 4 lanes of PCIE gen 4. Gen 6 will make it a lot easier to find room for a few 100gb/s ethernet connections which are always nice for faster server to server networking, as well as making it easier to use pcie only storage.

Internally passing around multiple 4k video outputs would use this. Maybe you don't want the output via the port on the back of the card but want to pass it through internally to some other peripheral? I think this is how thunderbolt ports work right (happy to be corrected)?

120hz star citizen

Reply on news.ycombinator.com